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VHDL - Generate sub-module (or not)

 
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Old 10-24-2006, 03:09 PM   #1
Default Generate sub-module (or not)


I'm designing a flash memory controller which will have a sub-block
dedicated to a special function.
I want to use a generic to either generate the sub-module or not, and
to tie what were sub-module outputs (inputs to the main flash mem
controller block) to a default level.

Is this possible?

I've only used generate (a long time ago, 1992!) to create a
daisy-chain of JTAG modules which were always wanted.

Not sure how to do what I want, but something like:

IF gen_special GENERATE
special_inst: special PORT MAP (...............);
ELSE -- illegal?

END GENERATE;

I could have a "null" sub-module with the required default port levels,
but how do I then generate either/or?

TIA, Kev P.



Niv
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Old 10-24-2006, 04:06 PM   #2
Niv
 
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Default Re: Generate sub-module (or not)

Niv wrote:
> I'm designing a flash memory controller which will have a sub-block
> dedicated to a special function.
> I want to use a generic to either generate the sub-module or not, and
> to tie what were sub-module outputs (inputs to the main flash mem
> controller block) to a default level.
>
> Is this possible?
>
> I've only used generate (a long time ago, 1992!) to create a
> daisy-chain of JTAG modules which were always wanted.
>
> Not sure how to do what I want, but something like:
>
> IF gen_special GENERATE
> special_inst: special PORT MAP (...............);
> ELSE -- illegal?
>
> END GENERATE;
>
> I could have a "null" sub-module with the required default port levels,
> but how do I then generate either/or?
>
> TIA, Kev P.


Sorted it myself (eventually).

Ta anyway,
Kev P.



Niv
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