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VHDL - addig delay to modelsim simulation |
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10-21-2006, 09:01 PM
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#1 |
addig delay to modelsim simulation
i have a vhdl code with testbanch for modelsim
i want to see the results of the simulation including delays i know that i can do *vho file whis quartus to add delayes to modelsim i tryed do this but without any sucsses can anyone help me please and describe how to do it thanks igal001 |
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