Synthesis

Hallo,

I have a question, I want to program Cypress PALCE20V8, with the following VHDL code. but I can not fit following code on the PALCE20V8, it needs more outputs than 8. But in my code, I have made it clear that the number of outputs is 7, so it should be fit on the PALCE20V8. Can this vhdl code be more optimized in the view of synthesis?

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LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY PAL IS
port(
Mode1,
Mode2,
Power_off,
Osc_input,
MAX_232_pin_9,
PULS,
Reset :IN Std_Logic;

EN5V,
EN10V,
Zener5V,
Osc_output,
PTA0_PAL,
PTA1_PAL,
PTA4_PAL :OUT Std_Logic
);
END ENTITY PAL;

--
ARCHITECTURE behavioral OF PAL IS
BEGIN
control: Process(Mode1, Mode2, Power_off, Osc_input, MAX_232_pin_9, PULS, Reset )
Begin
If (Mode1 = '0' AND Mode2 = '0' AND Power_off = '0') then
--Normal Mode
EN5V <= 'Z';
EN10V <= 'Z';
Zener5V <= PULS;
Osc_output <= 'Z';
PTA0_PAL <= PULS;
PTA1_PAL <= PULS;
PTA4_PAL <= NOT Reset;
elsif (Mode1 = '0' AND Mode2 = '0' AND Power_off = '1') then
--Power_off mode
EN5V <= '1';
EN10V <= 'Z';
Zener5V <= 'Z';
Osc_output <= 'Z';
PTA0_PAL <= 'Z';
PTA1_PAL <= 'Z';
PTA4_PAL <= 'Z';
elsif (Mode1 = '0' AND Mode2 = '1') then
--Mode 2
EN5V <= '0';
EN10V <= '0';
Zener5V <= '1';
Osc_output <= Osc_input;
PTA0_PAL <= MAX_232_pin_9;
PTA1_PAL <= 'Z';
PTA4_PAL <= 'Z';
elsif (Mode1 = '1') then
--Mode 1
EN5V <= '0';
EN10V <= '1';
Zener5V <= 'Z';
Osc_output <= Osc_input;
PTA0_PAL <= MAX_232_pin_9;
PTA1_PAL <= '1';
PTA4_PAL <= '0';
end if;
End Process;
END ARCHITECTURE behavioral;
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