KJ, your simple example might be misleading to a novice. The example
statement is synthesizable in the context that the synthesis tool
'ignores' the AFTER clause because the tool knows that portion of the
statement is not synthesizable at this point in time. This convenience
allows designers the ability to add representative delays into the RTL
to help with modeling while still allowing the synthesizer to build the
logic structures.
You are correct in saying that no synthesizer today can synthesize
logic to incorporate specific delay characteristics as in the example
given.
KJ wrote:
> "Moikel" <> wrote in message
> news: ps.com...
> > Hi,
> >
> > I have some experience with VHDL, but only once have commited a design
> > to programmable logic ( a Xilinx CPLD). It worked perfectly. However,
> > I'm hearing the phrase "synthesizable VHDL" being used a lot. This
> > implies to me that some VHDL code cannot be commited to hardware i.e.
> > is not synthesizable. Is this true? What exactly does 'synthesizable'
> > refer to? Could someone clarify this for me?
>
> Something is considered 'synthesizable' if it can be turned into a physical
> design. The code you wrote for your CPLD was synthesizable since there was
> a software tool (presumbably ISE) which was able to turn your VHDL source
> code into the proper sequence of bits that could then be programmed into a
> device which could be assembled on to a board and implement whatever
> function you had written for it.
>
> When it gets right down to it most everything you write 'could' be
> synthesized into real hardware but given limitations of technology might not
> be able to be synthesized into real hardware 'today' or even more
> specifically might not be able to be created in the device that you would
> like to use. Tomorrow's technology might not have such limitations so what
> can or can not be synthesized is a function of time as well as a function of
> specific device technologies. For example, most people in this newsgroup do
> FPGA/CPLD designs and in that environment using today's technology the
> following line of code would be a simple example of non-synthesizable code:
>
> x <= y after 2 ns;
>
> It would be considered non-synthesizable because most (perhaps even none) of
> today's FPGA/CPLD parts can generate something to implement the 2 ns delay.
> But that line of code is not totally unrealizable, in fact it is very old
> technology called a delay line. The above line of code can also be
> implemented inside an ASIC. Maybe 5 years from now, demand for delay lines
> in FPGAs will be great enough that they will start showing up there as well.
>
> KJ
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