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RFC on VHDL LRM 93[8.4.1]

 
 
Al
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      11-13-2006
Mike Treseler wrote:
> Mike Treseler wrote:
>
>
>>OK.

>
>
> overload example:
>
> http://home.comcast.net/~mike_tresel...c_overload.vhd
>
>
> -- Mike Treseler


I would like to inform you that your approach to testbench has
completely changed my way of working. It didn't take a lot after all to
get used to these procedures nesting and procedure overloading. My
testbench now look much easy to handle and even more efficient.

Still I didn't get enough confidence with records and how to share
common variables, but I will manage to work it out.

Thanks a lot
Al
--
Alessandro Basili
CERN, PH/UGC
Hardware Designer
 
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Mike Treseler
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      11-13-2006
Al wrote:

> I would like to inform you that your approach to testbench has
> completely changed my way of working. It didn't take a lot after all to
> get used to these procedures nesting and procedure overloading. My
> testbench now look much easy to handle and even more efficient.


Thanks for your kind remarks.
And thanks to Jonathan Bromley who first posted the
parameter overloading idea here several years ago.

> Still I didn't get enough confidence with records and how to share
> common variables, but I will manage to work it out.


As long as I can make it down the hill
with my skis still on, it doesn't matter that much
if I actually did everything the instructor just said

-- Mike Treseler
 
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Andy
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      11-13-2006

Jim Lewis wrote:
> ... Ok so I have suffered through more than one
> project using either Synopsys DC or FPGA compiler for an
> FPGA design. As a result, I tend to protect myself
> more than the coding style you enjoy affords.


Don't even get me started on the garbage I've had to put up with to get
reasonable results from DC and/or FC!

See there, my BP is already up!

Andy

 
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