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adding std_logic_vectors in vhdl

 
 
ohaqqi ohaqqi is offline
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      10-17-2006
For a command like this one:

C <= std_logic_vector(signed(A) + signed(B))

How does VHDL add the vectors? For example, If I wanted to synthesize this on an FPGA, would the compiler create an adder? Or does it use some other technique to add vectors?
Sorry if this is too much of a newbie question
 
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zty zty is offline
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      10-17-2006
i think the synthesis tool will add many adder depend on the length of your vector.


Quote:
Originally Posted by ohaqqi
For a command like this one:

C <= std_logic_vector(signed(A) + signed(B))

How does VHDL add the vectors? For example, If I wanted to synthesize this on an FPGA, would the compiler create an adder? Or does it use some other technique to add vectors?
Sorry if this is too much of a newbie question
 
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ohaqqi ohaqqi is offline
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Join Date: Oct 2006
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      10-17-2006
Quote:
Originally Posted by zty
i think the synthesis tool will add many adder depend on the length of your vector.
That makes sense, thanks.

Does it use ripple-carry or carry-look-ahead adders?
 
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Daniel Kho Daniel Kho is offline
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      10-18-2006
Quote:
Does it use ripple-carry or carry-look-ahead adders?
Different compilers synthesize the same code differently sometimes. I guess you can know how your particular FPGA would implement your code at the RTL level by looking at the RTL viewer if your vendor provides such an option.
 
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