VHDL sll shift question

I'm working on a small project, 16 bit shifter. When CODE = '10000', registe
r A must shift by integer value of register B -- this is why I made them bid
irectional ports. Here's some snippets:

libraries:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity alu16 is
port (A,B: inout std_logic_vector(15 downto 0);
CODE: in std_logic_vector(4 downto 0);
C: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end alu16;

I tried:

A <= A sll to_integer(signed(B)) when (CODE(4) = '1' and CODE(3) = '0' and C
ODE(2) = '0' and CODE(1) = '0' and CODE(0) = '0');

and get the same error:

** Error: alu16.vhd(40): No feasible entries for infix operator "sll".
** Error: alu16.vhd(40): Type error resolving infix expression "sll".

Any help for a VHDL newbie?

ohaqqi

[kadwadhp]

Hi Ohaqqi,
Even I am new to VHDL...But still as far as I Know sll is a bit operator and doesn't operate on STD_LOGIC_VECTORS.Try converting all operands to bit_vector .
Best Regards,
Kadwadhp

kadwadhp

[srishankar]

hi i am doing a pong game using vhdl. do you knw how to make the paddle and ball move simultaneously

srishankar

[Nirmala]

u can manually perform left shift operation...but code will be lengthy

Nirmala

[power_hf2005]

instead of using "sll" operator, u can use another way to solve your problem.
I was in problem with it, and I made a function for shiftleft (sll) to replace opeator sll. here is the code for SL. Good luck!( I'm a Vietnamese so my E is not good )
subtype vao is std_logic_vector(7 downto 0);
function sl(input: vao) return vao is
variable k: std_logic_vector(7 downto 0);
begin
for i in 1 to 7 loop
k(i):=input(i-1);
end loop;
k(0):=input(7);
return k;
end sl;

power_hf2005