Iterating through a STD_LOGIC_VECTOR

Hi,

I am working on a Sequence Detector for a 128-bit input and I am running into some problems. I am using a two process FSM and I my question is what data type can I use as an iterator to step through the different bits of my 128-bit input?

Example in PSEUDO-VHDL:

a : IN std_logic_vector (127 downto 0); -- the input I am using

case Current_State is

when S0 => 

my_output <= '0';
if a(the_iterator_i_seek) = '1' then
  next_state <= S1;
  <increment my iterator>
else
  next_state <= S0;
  <increment my iterator>

...............etc etc

I basically want to check the 127 bit -> 126 bit -> 125 bit -> ......... and step through my state machine based on what bits I am resolving during my checks.

If anyone can throw me some help, I would greatly appreciate as I have tried to solve this problem with a signal integer and a variable integer and I am am loosing my mind =(.

funktion