hard to make it generic

hi all

I need some help for making generic VHDL. Problem is following.

Design module has input port X, output port Y, and internal control
signal C, with following type.
X : array (0 to 2) of std_logic_vector (1 downto 0);
Y : array (0 to 2) of std_logic_vector (1 downto 0);
C : array (0 to 2) of std_logic_vector (1 downto 0);

Output 'Y' is determined by control signal 'C' and input 'X'.
For example,
consider possible cases for 'C' are only C(0)="00", C(0)="01",
C(1)="01", C(2)="10".
Y(0) <= X(0) when C(0) is "00"
Y(0) <= X(1) when C(0) is "01"
Y(1) <= X(1) when C(1) is "01"
Y(2) <= X(2) when C(2) is "10"

In VHDL, I did it asynchronously and manually, depending on possible
'C' values.

Y( 0 ) <= X( 0 ) when C( 0 )="00" else
X( 1 ) when C( 0 )="01" else "00" ;
Y( 1 ) <= X( 1 ) when C( 1 )="01" else "00" ;
Y( 2 ) <= X( 2 ) when C( 2 )="10" else "00" ;

Then it works fine.
Problem is that I can not make thse VHDL descriptions "generic", when
possible values of 'C' are known.
For example, possible values C(1) are "00" and "01".
I don't want to use 3 MUXs to accomodate all possible cases.

Does someone has comment to do that ? Thankyou.

Pasacco

Pasacco wrote:
<snip>
> In VHDL, I did it asynchronously and manually, depending on possible
> 'C' values.
>
> Y( 0 ) <= X( 0 ) when C( 0 )="00" else
> X( 1 ) when C( 0 )="01" else "00" ;
> Y( 1 ) <= X( 1 ) when C( 1 )="01" else "00" ;
> Y( 2 ) <= X( 2 ) when C( 2 )="10" else "00" ;
>
> Then it works fine.
That's good!

> Problem is that I can not make thse VHDL descriptions "generic", when
> possible values of 'C' are known.
> For example, possible values C(1) are "00" and "01".
> I don't want to use 3 MUXs to accomodate all possible cases.
Why not? If you're concerned about logic resources being 'wasted'
inside a device then don't be. If it turns out that C(0) or C(1)
happen to be constants as you mentioned than any synthesis tool will
immediately catch on to this and optomize your code for the particular
values that C(0) and C(1) actually have and the 'mux' will collapse
right down into the exact same logic as if you had coded it ahead of
time knowing this.

It appears to me that what you have right now is the 'generic' solution
so don't be afraid to turn the synthesis tool loose on it with your
constants and watch the specific solution reduce down to exactly what
it should. Try it.

KJ

Thankyou for comment.

As you mentioned, MUXs are generic but I want to avoid 3 MUXs in order
to reduce logic.
Meanwhile, possible values of control signal 'C' are "known", but
internally "generated" instead of "constant".

I tried (1) full MUX generic implementation (2) manual implementation.
(2) is better than (1).
But I hope it is possible to avoid 3 MUXs, while keeping it generic.

I am trying to use look-up table buffer to contain possible values of
'C', since we already know possible values of 'C'. And I am trying to
make "conditional assignments statements" generic. But it is not easy.
Does anyone have comment? thankyou.

"Pasacco" <> wrote in message
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> Thankyou for comment.
>
> As you mentioned, MUXs are generic but I want to avoid 3 MUXs in order
> to reduce logic.
As I said with any reasonable synthesis tool, it won't reduce logic.

> Meanwhile, possible values of control signal 'C' are "known", but
> internally "generated" instead of "constant".
What is the difference between "known", but internally "generated" and
"constant"? If it's 'known' then you should be able to tell the synthesis
tool this in your code. Note, 'constants' can actually be quite complicated
VHDL functions that go through entire lots of lines of code to figure out
what that constant is. You might want to post some code showing a bit more
about how C() is generated and demonstrate the difference between "known",
but internally "generated" and "constant".

>
> I tried (1) full MUX generic implementation (2) manual implementation.
> (2) is better than (1).
Then your manual implementation is not implementing the same function as
your full mux implementation. The difference might come down to C() being
treated as a signal in #1 but a constant in #2 or it might be something else
but bottom line is they are doing something different.

> But I hope it is possible to avoid 3 MUXs, while keeping it generic.
>
> I am trying to use look-up table buffer to contain possible values of
> 'C', since we already know possible values of 'C'. And I am trying to
> make "conditional assignments statements" generic. But it is not easy.
> Does anyone have comment? thankyou.
Post some code demonstrating #1 and #2 Not sure how a lookup table of
possible C() values will help either but again posting some code would help

KJ