Frequency Divider Simulation problem using ModelSIM

Hello,

I am fairly new to VHDL although I have been working with HDL for a few
months. I have a homework assignment and part of it is to design a
freq. divider and a testbench and run simulation on it. I am using
ModelSIM for entry and simulation.

The code for the freq. divider I have taken out of the book, obviously
modified it to fit my solution and it compiles fine. The testbench
code has been taken from a class example, it only one line of code and
seems to generate the appropriate clock signal.

However, when I simulate I get no output on the clkdiv buffer (the
divided output). It stays at "U" the entire length of the simulation.

Below is my code. Any suggestions/pointers, etc are appreciated.

================================================== =================
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

--ENTITY
ENTITY genFreqDiv IS
GENERIC(
n: INTEGER := 2);
PORT(
clk: in std_logic;
clkdiv: buffer std_logic
);
END genFreqDiv;

--ARCHITECTURE
ARCHITECTURE genFreqDiv_arch OF genFreqDiv IS
BEGIN
PROCESS (clk)
VARIABLE counter: INTEGER RANGE 0 to 7;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
counter := counter + 1;
IF (counter = n) THEN
clkdiv <= NOT(clkdiv);
counter := 0;
END IF;
END IF;
END PROCESS;
END genFreqDiv_arch;

---------------------------------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

--ENTITY
ENTITY genFreqDiv_tb IS
END genFreqDiv_tb;

--ARCHITECTURE
ARCHITECTURE genFreqDiv_tb_arch OF genFreqDiv_tb IS
--Component Declaration
COMPONENT genFreqDiv
PORT(
clk: in std_logic;
clkdiv: buffer std_logic
);
END COMPONENT;

CONSTANT clkperiod: TIME := 10 ns;
SIGNAL test_clk: std_logic := '0';

BEGIN
UUT: genFreqDiv
PORT MAP(
clk => test_clk);

test_clk <= NOT test_clk AFTER clkperiod/2; --CLK Generation

END genFreqDiv_tb_arch;

Kyle H.

Hi,

The problem is you clkdiv is not initialized, which mean its value is 'U'
and not 'U' equal to 'U', so it always stay at 'U'.
The solution is to initialize this signal in the port declaration for
example:
clkdiv: buffer std_logic:='0'

Serge

"Kyle H." <> a écrit dans le message de news:
om...
> Hello,
>
> I am fairly new to VHDL although I have been working with HDL for a few
> months. I have a homework assignment and part of it is to design a
> freq. divider and a testbench and run simulation on it. I am using
> ModelSIM for entry and simulation.
>
> The code for the freq. divider I have taken out of the book, obviously
> modified it to fit my solution and it compiles fine. The testbench
> code has been taken from a class example, it only one line of code and
> seems to generate the appropriate clock signal.
>
> However, when I simulate I get no output on the clkdiv buffer (the
> divided output). It stays at "U" the entire length of the simulation.
>
> Below is my code. Any suggestions/pointers, etc are appreciated.
>
> ================================================== =================
> LIBRARY IEEE;
> USE IEEE.std_logic_1164.all;
>
> --ENTITY
> ENTITY genFreqDiv IS
> GENERIC(
> n: INTEGER := 2);
> PORT(
> clk: in std_logic;
> clkdiv: buffer std_logic
> );
> END genFreqDiv;
>
> --ARCHITECTURE
> ARCHITECTURE genFreqDiv_arch OF genFreqDiv IS
> BEGIN
> PROCESS (clk)
> VARIABLE counter: INTEGER RANGE 0 to 7;
> BEGIN
> IF (clk'EVENT AND clk = '1') THEN
> counter := counter + 1;
> IF (counter = n) THEN
> clkdiv <= NOT(clkdiv);
> counter := 0;
> END IF;
> END IF;
> END PROCESS;
> END genFreqDiv_arch;
>
> ---------------------------------------------------------------------------------------------------------------------------
> LIBRARY IEEE;
> USE IEEE.std_logic_1164.all;
>
> --ENTITY
> ENTITY genFreqDiv_tb IS
> END genFreqDiv_tb;
>
> --ARCHITECTURE
> ARCHITECTURE genFreqDiv_tb_arch OF genFreqDiv_tb IS
> --Component Declaration
> COMPONENT genFreqDiv
> PORT(
> clk: in std_logic;
> clkdiv: buffer std_logic
> );
> END COMPONENT;
>
> CONSTANT clkperiod: TIME := 10 ns;
> SIGNAL test_clk: std_logic := '0';
>
> BEGIN
> UUT: genFreqDiv
> PORT MAP(
> clk => test_clk);
>
> test_clk <= NOT test_clk AFTER clkperiod/2; --CLK Generation
>
> END genFreqDiv_tb_arch;
>

Initialise 'clkdiv' to a value at the start, otherwise the assignment
"clkdiv <= NOT clkdiv" will yield an unknown result.

----------------------------------
ENTITY genFreqDiv IS
GENERIC(
n: INTEGER := 2);
PORT(
clk: in std_logic;
clkdiv: buffer std_logic := '0'
);
END genFreqDiv;
---------------------------------

Hope that helps
Matt

Serge & Matt,

Thanks so much for your help. I had thought that might be an issue,
but the book doesn't have it! So I thought it should work.

Thanks again,
Kyle