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help for a beginner

 
 
mike-t
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      09-24-2006
Can anyone help me figure out how to connect these three ports.

I have a port - dataio : inout std_logic_vector (15 downto 0);
I would like to connect the following ports to it:

sdatao : out std_logic_vector (7 downto 0);
sdatai : in std_logic_vector (7 downto 0);


any help would be appreciated.

 
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Paul Uiterlinden
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      09-24-2006
mike-t wrote:

> Can anyone help me figure out how to connect these three ports.
>
> I have a port - dataio : inout std_logic_vector (15 downto 0);
> I would like to connect the following ports to it:
>
> sdatao : out std_logic_vector (7 downto 0);
> sdatai : in std_logic_vector (7 downto 0);
>
>
> any help would be appreciated.


Just connect them together. Like in real hardware, the trick is of
course preventing two outputs driving (non-'Z') at the same time. So
you must have some direction/enable inputs on the blocks that have
the dataio and sdatao outputs.

--
Paul.

 
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mike-t
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      09-24-2006
Paul, thanks for the guidance..

I tryied the following port map:
sdatao <= dataio (7 downto 0)
sdatai <= dataio (15 downto

this didnt work....


Paul Uiterlinden wrote:
> mike-t wrote:
>
> > Can anyone help me figure out how to connect these three ports.
> >
> > I have a port - dataio : inout std_logic_vector (15 downto 0);
> > I would like to connect the following ports to it:
> >
> > sdatao : out std_logic_vector (7 downto 0);
> > sdatai : in std_logic_vector (7 downto 0);
> >
> >
> > any help would be appreciated.

>
> Just connect them together. Like in real hardware, the trick is of
> course preventing two outputs driving (non-'Z') at the same time. So
> you must have some direction/enable inputs on the blocks that have
> the dataio and sdatao outputs.
>
> --
> Paul.


 
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mike-t
Guest
Posts: n/a
 
      09-24-2006
Paul, thanks for the guidance..

I tryied the following port map:
sdatao <= dataio (7 downto 0)
sdatai <= dataio (15 downto

this didnt work....


Paul Uiterlinden wrote:
> mike-t wrote:
>
> > Can anyone help me figure out how to connect these three ports.
> >
> > I have a port - dataio : inout std_logic_vector (15 downto 0);
> > I would like to connect the following ports to it:
> >
> > sdatao : out std_logic_vector (7 downto 0);
> > sdatai : in std_logic_vector (7 downto 0);
> >
> >
> > any help would be appreciated.

>
> Just connect them together. Like in real hardware, the trick is of
> course preventing two outputs driving (non-'Z') at the same time. So
> you must have some direction/enable inputs on the blocks that have
> the dataio and sdatao outputs.
>
> --
> Paul.


 
Reply With Quote
 
mike-t
Guest
Posts: n/a
 
      09-24-2006
Paul, thanks for the guidance..

I tryied the following port map:
sdatao <= dataio (7 downto 0)
sdatai <= dataio (15 downto

this didnt work....


Paul Uiterlinden wrote:
> mike-t wrote:
>
> > Can anyone help me figure out how to connect these three ports.
> >
> > I have a port - dataio : inout std_logic_vector (15 downto 0);
> > I would like to connect the following ports to it:
> >
> > sdatao : out std_logic_vector (7 downto 0);
> > sdatai : in std_logic_vector (7 downto 0);
> >
> >
> > any help would be appreciated.

>
> Just connect them together. Like in real hardware, the trick is of
> course preventing two outputs driving (non-'Z') at the same time. So
> you must have some direction/enable inputs on the blocks that have
> the dataio and sdatao outputs.
>
> --
> Paul.


 
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Paul Uiterlinden
Guest
Posts: n/a
 
      09-24-2006
mike-t wrote:

> Paul, thanks for the guidance..
>
> I tryied the following port map:
> sdatao <= dataio (7 downto 0)
> sdatai <= dataio (15 downto


Why 15 downto 8? Oh wait, now I see. You wrote:

> I have a port - dataio : inout std_logic_vector (15 downto 0);
>*I*would*like*to*connect*the*following*ports*to*it:
>
> sdatao : out std_logic_vector (7 downto 0);
> sdatai : in std_logic_vector (7 downto 0);


I missed the point that the inout port is 16 bits wide and the two
other ports 8 bits.

So what exactly do you want to achieve? What are the requirements?
Does it involve three components, like this?:

component_1 dataio --<->--15:0--+---15:8--<-- sdatao component_2
|
+----7:0-->-- sdati component_3
> this didnt work....


That's not a very exact descriprion, is it? What did you do, what did
you see, what did you expect?

--
Paul.

 
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