Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Call for Participation Accellera VHDL Verification Features

Thread Tools

Call for Participation Accellera VHDL Verification Features

Jim Lewis
Posts: n/a
If you have strong verification skills and have used
a language such as SystemVerilog, e, Vera, or SystemC
for verification and would like to be able to use
VHDL, you should be participating in the Accellera
VHDL enhancments effort.

Some of the tasks on our list are adding OO, interfaces,
constrained random, functional coverage, verification
data structures, ...

You do not need to be an Accellera member to participate.
Go to the webpage

Under join here, select the appropriate "click here"
link (Accellera member vs. non-member).

Non-Accellera members fill in your name and information
and send the request to Lynn Horobin, Administration & Marketing.
In the big text box, ask to join Accellera VHDL TSC,
VHDL Extensions subcommittee, and VHDL Requirements subcommittee.

Note that most decisions are made by consensus of all
participants. Only contentious items are decided by a
member based vote. In the last revision, I think there
were only 3 of over 100 items resolved this way.

Of course for those of you who belong to companies with
sufficient resources, membership in Accellera will help
fund the effort (mainly LRM editing task) and is greatly

Best Regards,
Jim Lewis
VHDL and VHDL Standards Evangalist

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc.

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Reply With Quote
Posts: n/a
I subscribed/sent an email via that page showing interest, didn't
hear back anything from anyone from the commitee? Is there another
channel that I should pursue?


Reply With Quote
Chris Foster
Posts: n/a
Jim Lewis <(E-Mail Removed)> wrote in news:12h8ur17fq16r39


I signeed up as you asked at MAPLD. We will se how far I get without
your assistance

Chris Foster

Posted via a free Usenet account from

Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Breaking News ... Accellera Verification Working Group Forming VHDL 8 05-21-2008 08:58 PM
Accellera Approves VHDL 4.0 Amal VHDL 0 02-27-2008 06:21 PM
Accellera VHDL 2006 LRM Amal VHDL 7 06-20-2007 01:58 AM
VHDL Standards Overview of Accellera VHDL 2006 Standard 3.0 Jim Lewis VHDL 0 10-13-2006 09:24 PM
Accellera, OVL, and VHDL? geocon VHDL 2 10-06-2005 06:54 PM