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VHDL - doubt in variable passing in multiple process

 
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Old 09-22-2006, 06:08 AM   #1
Default doubt in variable passing in multiple process


let me say

i am having two processes
process(clk1) and process(clk2)


process(clk1)
variable x:natural:=0;
begin
if clk'event and clk='1' then
x := x+1;
end if
end process;

process(clk2)
begin
----
-------
-----
end process

in the 1st process x may be changed to some 10 let me say.
and i want that variable with changed value to be utilized in 2nd
process how can i do it.
if i declare variable x before process1 it is giving error that shared
variables only should be declared here.
thank you



chaitanyakurmala@gmail.com
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Old 09-22-2006, 06:12 AM   #2
David Ashley
 
Posts: n/a
Default Re: doubt in variable passing in multiple process

wrote:
> let me say
>
> i am having two processes
> process(clk1) and process(clk2)
>
>
> process(clk1)
> variable x:natural:=0;
> begin
> if clk'event and clk='1' then
> x := x+1;
> end if
> end process;
>
> process(clk2)
> begin
> ----
> -------
> -----
> end process
>
> in the 1st process x may be changed to some 10 let me say.
> and i want that variable with changed value to be utilized in 2nd
> process how can i do it.
> if i declare variable x before process1 it is giving error that shared
> variables only should be declared here.
> thank you
>


Dude there's gotta be a better way of learning the language. This
is too much hand holding, these are fundamental things in VHDL.
Read your book, work the examples. It's all there...

-Dave

--
David Ashley http://www.xdr.com/dash
Embedded linux, device drivers, system architecture
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Old 09-22-2006, 07:56 AM   #3
alessandro basili
 
Posts: n/a
Default Re: doubt in variable passing in multiple process

Variable declared in a process are only available for that process. I
think you better study some more basics before approaching any project.

wrote:
> let me say
>
> i am having two processes
> process(clk1) and process(clk2)
>
>
> process(clk1)
> variable x:natural:=0;
> begin
> if clk'event and clk='1' then
> x := x+1;
> end if
> end process;
>
> process(clk2)
> begin
> ----
> -------
> -----
> end process
>
> in the 1st process x may be changed to some 10 let me say.
> and i want that variable with changed value to be utilized in 2nd
> process how can i do it.
> if i declare variable x before process1 it is giving error that shared
> variables only should be declared here.
> thank you
>

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Old 09-22-2006, 09:35 PM   #4
Paul Uiterlinden
 
Posts: n/a
Default Re: doubt in variable passing in multiple process

wrote:

> let me say
>
> i am having two processes
> process(clk1) and process(clk2)
>
>
> process(clk1)
> variable x:natural:=0;
> begin
> if clk'event and clk='1' then
> x := x+1;
> end if
> end process;
>
> process(clk2)
> begin
> ----
> -------
> -----
> end process
>
> in the 1st process x may be changed to some 10 let me say.
> and i want that variable with changed value to be utilized in 2nd
> process how can i do it.


Use a signal. Signals are the normal way for communication between
processes.

> if i declare variable x before process1 it is giving error that
> shared variables only should be declared here.
> thank you


Variables declared outside a process must be declared shared. But stay
away from shared variables as a beginner. With shared variables it is
possible to create non-deterministic behavior. So for now stay clear.
First learn the fundamentals of VHDL.

--
Paul.
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Old 10-02-2006, 08:32 PM   #5
Mike Treseler
 
Posts: n/a
Default Re: doubt in variable passing in multiple process

Paul Uiterlinden wrote:

> Use a signal. Signals are the normal way for communication between
> processes.


Or do all of the logic using the variable x_v in the same process.
A process port assignment like
my_port <= x_v;
will then do the job without any interposed signals.

-- Mike Treseler
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