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VHDL - Missing direction on entity port

 
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Old 09-22-2006, 04:37 AM   #1
Default Missing direction on entity port


As a result of changing what was a generic to an input port, I omitted the
keyword 'in'. Neither the simulator (Modelsim 6.x) nor the synthesis tool
(Synplicity 8.4) challenged me on this. Is there a specified default? Or
is this a tool thing? (In case it isn't obvious, both the simulation and the
synthesis turned out okay.)

Jason




jtw
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Old 09-22-2006, 09:26 PM   #2
Paul Uiterlinden
 
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Default Re: Missing direction on entity port

jtw wrote:

> As a result of changing what was a generic to an input port, I
> omitted the
> keyword 'in'. Neither the simulator (Modelsim 6.x) nor the
> synthesis tool
> (Synplicity 8.4) challenged me on this. Is there a specified
> default? Or is this a tool thing? (In case it isn't obvious, both
> the simulation and the synthesis turned out okay.)


The mode is optional with IN as default. The same goes for the formal
parameters in the parameter list declaration of subprograms
(procedures and functions). So it is perfectly OK that the simulator
and synthesizer do not complain.

--
Paul.

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