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VHDL - Missing direction on entity port |
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#1 |
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As a result of changing what was a generic to an input port, I omitted the
keyword 'in'. Neither the simulator (Modelsim 6.x) nor the synthesis tool (Synplicity 8.4) challenged me on this. Is there a specified default? Or is this a tool thing? (In case it isn't obvious, both the simulation and the synthesis turned out okay.) Jason jtw |
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#2 |
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Posts: n/a
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jtw wrote:
> As a result of changing what was a generic to an input port, I > omitted the > keyword 'in'. Neither the simulator (Modelsim 6.x) nor the > synthesis tool > (Synplicity 8.4) challenged me on this. Is there a specified > default? Or is this a tool thing? (In case it isn't obvious, both > the simulation and the synthesis turned out okay.) The mode is optional with IN as default. The same goes for the formal parameters in the parameter list declaration of subprograms (procedures and functions). So it is perfectly OK that the simulator and synthesizer do not complain. -- Paul. |
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