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VHDL - to alessandro basili

 
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Old 09-21-2006, 09:50 AM   #1
Default to alessandro basili


no in the fifo program when all fifo buffers are filled we will have
fifo-index=16
then after data in 1st buffer is transfered to 2nd clock domain( always
data in 1st buffer is transfered to second clock domain).the data in
2nd buffer should be moved to first , data in 3rd to 2nd and so on..
data in 16 th to 15th totally 15 movements . so i decremented fifo
index by 1 to make it 15. and in that program i am making 15
translations of data . so fifo-index=15.
and i=1
fifo_buffer(1)=fifo_buffer(2);(fifo_buffer(i)=fifo _buffer(i+1))
i=1+1;
if(i =15+1)
exit loop;
end if;
so until i=15 loop rotates as fifo_buffer(15)=fifo_buffer(16);
then i=1+1 =>i=16
and if condition satisfies and loop exits..this is ok na.
even though if condition is modified i am getting same error
Index value <17> is not in Range of array <fifo_buffer>.



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