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sensitivity list confusion

 
 
traxx84 traxx84 is offline
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Join Date: Sep 2006
Posts: 1
 
      09-25-2006
Hi all....i am student learning the VHDL coding this semester.....recently i found that the process statement with its sensitivity list does not work the way it is said in the text book.....although i never insert a particular signal into the sensitivity list....the output is changes whenever the particular signal changes value...... for example

-- h
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity h is
port (
d : out STD_LOGIC;
c : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC
);
end h;

architecture h_arch of h is
begin
process(a)
begin

d<=a and b and c;


end h_arch;


the d value changes each time the value of either b or c changes although i mantain the value of a...

Can anybody help me in this problem???

Thanx!!!!!!!
 
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eesuperstar eesuperstar is offline
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Join Date: Nov 2012
Posts: 1
 
      11-14-2012
I know this is super old but was this ever solved?
 
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