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VHDL - Error in variable assignment

 
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Old 09-20-2006, 02:47 PM   #1
Default Error in variable assignment


Hi,

I want to assign a value to variable and then use this value for assigning for a signal. Such as

c<= (a and b) or (d:= a and b);

but its giving me an error

near ":=": expecting: ')'
near ")": expecting: ';'

can anyone suggest me the solution.

Thank you.


veenamgp
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