Simple design with MICROBLAZE in Virtex 4

Hi,

I have created a simple design using Microblaze, FSL bus (connect Microblze and custom IP) and custom IP ( to receive data from Microblaze). This design is created in EDK 8.1. I moved to ISE 8.1 when my design was ready for implementation.

In ISE, I have verified my design by "behaviral simulation" and I got expacted result. Then I have successfully generated "system_stub.bit" file (My top level file name in ISE is "system_stub.vhd").

Now I thought to check my design with "Post-translate Simulation" but I don't know how to creat a test bench for the top level file named as "system_stub_translate.vhd".

system_stub_translate.vhd lokks like this .....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity lmb_bram_elaborate is
port (
BRAM_Clk_A : in STD_LOGIC := 'X';
BRAM_Clk_B : in STD_LOGIC := 'X';
BRAM_Rst_A : in STD_LOGIC := 'X';
BRAM_Rst_B : in STD_LOGIC := 'X';
BRAM_EN_A : in STD_LOGIC := 'X';
BRAM_EN_B : in STD_LOGIC := 'X';
BRAM_Addr_A : in STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Addr_B : in STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Dout_A : in STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Dout_B : in STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_WEN_A : in STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_WEN_B : in STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Din_B : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : out STD_LOGIC_VECTOR ( 0 to 31 )
);
end lmb_bram_elaborate;

architecture Structure of lmb_bram_elaborate is
...................
..........

So, I don't know how to creat a test file for this kind of interface (BRAM).
Any one can guide me how to check the system OUTPUT between Synthesis and .bit file generation ??

I will appreciate ur little effort.

Thanks

Saurin

saurinjpatel