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[Lesalesa]

Hello Everyone,

I was working in the simulation..
I have verilog TB and VHDL instance..When I try to simulate..Modelsim gives unresolved reference error.

example:

DATA = tb.U1.U2.U3.ram[addr_tmp[ADDRWID1:1]]:

U1 - testbench instance Name(dut).
U2,U3 - VHDL insntance(DUT Model instances)
ram is the signal with array type declaraion.

In the tb(VERILOG) trying to access the 2-dimentional array available in VHDL(Instance)..

If my instance is verilog no issues..when it comes to vhdl ,simulator gives error. So can you anyone give me the reason why its failing..Thanks in Advance..

-Sathish