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VHDL - inout

 
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Old 09-16-2006, 08:06 PM   #1
Default inout


inout port triggers self?


Attila Csosz
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Old 09-16-2006, 11:05 PM   #2
Paul Uiterlinden
 
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Attila Csosz wrote:

> inout port triggers self?


Processes are triggered, not ports.

--
Paul.
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Old 09-16-2006, 11:42 PM   #3
Attila Csosz
 
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Default Re: inout

But u understand what I mean..

Paul Uiterlinden wrote:
> Attila Csosz wrote:
>
>> inout port triggers self?

>
> Processes are triggered, not ports.
>

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Old 09-17-2006, 03:29 PM   #4
Paul Uiterlinden
 
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Default Re: inout

Attila Csosz wrote:

> Paul Uiterlinden wrote:
>> Attila Csosz wrote:
>>
>>> inout port triggers self?

>>
>> Processes are triggered, not ports.
>>

> But u understand what I mean..
>


No, I don't see what inout ports has to do with it.

Simplest self-triggering process:

clk <= NOT clk AFTER 1 ns;

Any other process that assigns to a signal that is also in the
sensitivity list or wait clause triggers itself. Whether the signal
is a formal port of mode inout is irrelevant.

--
Paul.

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