Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > pipeline machine construction set

Thread Tools

pipeline machine construction set

Posts: n/a
I wonder If there is something like that available somewhere?

I often have to deal with iterational and sequential pipeline
processes, beeing fed by e.g. arrays and then doing some mathematical
operations which require a number of states to be finished. Setting up
the machines I usally draw an excel sheet clarifying the points of time
when a certain result is present and where it is processed.

For many reasons, it is sometime necessary to change some actions
because of calculation parts, which need mre clocks or multicycle
delays resulting in a huge amount of work to do recoding: Formerly
concurrent actions have partly to be moved to other pipeline stages,
dependencies have to be updated.

How to you do this?

How do you create reasonable documentation for this, so others can
understand the processes?

I have such an Excelsheet prepared to show, what I mean - but do not
know how to upload it. Please drop me a mail in case you are interested

Reply With Quote
Posts: n/a
I've thougth about this before, but have not had a chance to try it.

What if you created a record type with elements for all your input,
internal, and output values. Then create an array of this record with
as many elements as pipeline stages needed. (if you need to add,
delete, or change a signal, you just change the definition of the
record type, the rest is handled automatically)

Then, in the following order:

Load stage 0 with input (dummy values for internals, outputs)

Use a For loop to automatically advance stage 0 -> 1, 1->2, etc. by

Or, if d is the array, then:
d <= (ina, inb, en, 0, 0) & d(0 to numpipes - 2); -- load and advance
pipeline by default

perform specific functions between explicit pipeline stages

e.g. stage 1 of "sum" gets loaded with ina + inb from stage 0:
d(1).sum <= d(0).ina + d(0).inb;

Assign outputs from last stage of pipe.

You're done.

Sure, an awful lot of registers will get created, then optimized out,
but the code will be pretty easy to understand functionally, and you
have the documenational advantage of what is happening in which stage.

Another thing to try, depending on the "retiming", or "register
balancing", ablilties of your synthesis tool, is to just code up the
function you want, all in one clock cycle, then send the output(s)
through a string of registers, and let the synthesis tool redistribute
the logic amongst the registers (or registers amongst the logic, if you


Reply With Quote
Posts: n/a
Hi Andy,

in fact two fine ideas!

The first one seems to be the academically greater challange and should
be my choice since I prefer, to keep control over the synthesis result
as far as possible (i am a register related old school designer

But I will give also the other one a chance. I think it will work with
most architectures using multi cycle constraints, but I also use
pipelined deviders which are somehow fixed to certain ins and outs of
the concurrent pipe. Hm, let's see. I will post a result.

Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
How to describe a pipeline structure in VHDL Ingmar Seifert VHDL 10 11-04-2009 07:25 AM
Construction of a non-regexable subset of the set of all strings Dominic van der Zypen Perl Misc 3 06-23-2006 02:52 PM
Default construction versus construction with initial values Ook C++ 10 10-08-2005 09:00 PM
vhdl for data forwarding in a pipeline machine Eqbal Z VHDL 1 10-09-2003 06:25 PM