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VHDL Standards Progress Report

 
 
Jim Lewis
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Posts: n/a
 
      09-14-2006
IEEE VHDL Analysis and Standardization Group (VASG) is the
IEEE working group responsible for maintaining and extending
the VHDL standard (IEEE 1076). Currently VASG is collaborating
with the Accellera VHDL Technical Subcommittee (VHDL TSC) to
accomplish this task.

I have just updated the VASG webpage updates regarding
status of VHDL standards revisions (both within Accellera
and IEEE). For details see: http://www.eda-stds.org/vasg
The older page, http://www.eda-stds.org/vhdl-200x/
has been merged with the vasg page.
Note also that any of the following domains are aliases to
the same information: eda.org, eda-stds.org, vhdl.org


I will also summarize (or restate) the status below:


_VHDL + VHPI_
On June 28, 2006 Accellera board approved a revision of
1076 that includes VHDL + VHPI (VHDL Procedural Language
Application Interface) + minor LRM maintence. Currently
this draft is working its way through IEEE standardization.


_VHDL + VHPI + VHDL-200X/VHDL-200X-FT + additional enhancements_
At DAC 2006 the Accellera board approved an enhanced
revision of 1076 that is VHDL + VHPI + enhancements.
The IEEE VASG started the work in early 2003 as VHDL-200X.
The Accellera VHDL Technical Subcommittee took over the
work in 2005, funded its technical editing, and did
super-human work to finalize it. In the near future
an Accellera press release will announce this
accomplishment.

As an Accellera standard, this version is available
for industry adoption - so let your vendors know you
want it. In fact, the claim is that since Accellera
standards are user driven, vendors are more willing to
implement the standard features since they know the
features are things desired and requested by users.
This was demonstrated in the implementation of
SystemVerilog (which started as an Accellera
standard).

I will be presenting a paper at Mentor's MARLUG on
October 12th that details the changes. After that
date the slides will be available at:
http://www.synthworks.com/papers/

Currently there are some older papers on that webpage
that reflect the intent at the time they were written.


_Accellera VHDL 2007_
The Accellera VHDL TSC is continuing its work to
enhance VHDL. Current items being worked on include
constrained random, coverage, OO, interfaces, and
verification data structures (associative arrays,
memories, ...). When this work is completed, it
will give VHDL similar verification capability to
SystemVerilog.


Join us and help create the next VHDL standards.
Your support (either financial or participation or both)
is greatly appreciated. For details see:
http://www.eda-stds.org/vasg/#Participation


By the way, if you have not checked the Accellera webpage
recently, you will notice that VHDL is also listed
prominently on the home page. See:
http://www.accellera.org/home


Best Regards,
Jim Lewis
IEEE VASG Chair
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
 
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Hans
Guest
Posts: n/a
 
      09-14-2006
Thanks Jim,

It is good to see that VHDL is still actively being worked on,

Regards,
Hans.
www.ht-lab.com


"Jim Lewis" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> IEEE VHDL Analysis and Standardization Group (VASG) is the
> IEEE working group responsible for maintaining and extending
> the VHDL standard (IEEE 1076). Currently VASG is collaborating
> with the Accellera VHDL Technical Subcommittee (VHDL TSC) to
> accomplish this task.
>
> I have just updated the VASG webpage updates regarding
> status of VHDL standards revisions (both within Accellera
> and IEEE). For details see: http://www.eda-stds.org/vasg
> The older page, http://www.eda-stds.org/vhdl-200x/
> has been merged with the vasg page.
> Note also that any of the following domains are aliases to
> the same information: eda.org, eda-stds.org, vhdl.org
>
>
> I will also summarize (or restate) the status below:
>
>
> _VHDL + VHPI_
> On June 28, 2006 Accellera board approved a revision of
> 1076 that includes VHDL + VHPI (VHDL Procedural Language
> Application Interface) + minor LRM maintence. Currently
> this draft is working its way through IEEE standardization.
>
>
> _VHDL + VHPI + VHDL-200X/VHDL-200X-FT + additional enhancements_
> At DAC 2006 the Accellera board approved an enhanced
> revision of 1076 that is VHDL + VHPI + enhancements.
> The IEEE VASG started the work in early 2003 as VHDL-200X.
> The Accellera VHDL Technical Subcommittee took over the
> work in 2005, funded its technical editing, and did
> super-human work to finalize it. In the near future
> an Accellera press release will announce this
> accomplishment.
>
> As an Accellera standard, this version is available
> for industry adoption - so let your vendors know you
> want it. In fact, the claim is that since Accellera
> standards are user driven, vendors are more willing to
> implement the standard features since they know the
> features are things desired and requested by users.
> This was demonstrated in the implementation of
> SystemVerilog (which started as an Accellera
> standard).
>
> I will be presenting a paper at Mentor's MARLUG on
> October 12th that details the changes. After that
> date the slides will be available at:
> http://www.synthworks.com/papers/
>
> Currently there are some older papers on that webpage
> that reflect the intent at the time they were written.
>
>
> _Accellera VHDL 2007_
> The Accellera VHDL TSC is continuing its work to
> enhance VHDL. Current items being worked on include
> constrained random, coverage, OO, interfaces, and
> verification data structures (associative arrays,
> memories, ...). When this work is completed, it
> will give VHDL similar verification capability to
> SystemVerilog.
>
>
> Join us and help create the next VHDL standards.
> Your support (either financial or participation or both)
> is greatly appreciated. For details see:
> http://www.eda-stds.org/vasg/#Participation
>
>
> By the way, if you have not checked the Accellera webpage
> recently, you will notice that VHDL is also listed
> prominently on the home page. See:
> http://www.accellera.org/home
>
>
> Best Regards,
> Jim Lewis
> IEEE VASG Chair
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
> Jim Lewis
> Director of Training (E-Mail Removed)
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL Training for Hardware Design and Verification
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~



 
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Weng Tianxiang
Guest
Posts: n/a
 
      09-14-2006

Jim Lewis wrote:
> IEEE VHDL Analysis and Standardization Group (VASG) is the
> IEEE working group responsible for maintaining and extending
> the VHDL standard (IEEE 1076). Currently VASG is collaborating
> with the Accellera VHDL Technical Subcommittee (VHDL TSC) to
> accomplish this task.
>
> I have just updated the VASG webpage updates regarding
> status of VHDL standards revisions (both within Accellera
> and IEEE). For details see: http://www.eda-stds.org/vasg
> The older page, http://www.eda-stds.org/vhdl-200x/
> has been merged with the vasg page.
> Note also that any of the following domains are aliases to
> the same information: eda.org, eda-stds.org, vhdl.org
>
>
> I will also summarize (or restate) the status below:
>
>
> _VHDL + VHPI_
> On June 28, 2006 Accellera board approved a revision of
> 1076 that includes VHDL + VHPI (VHDL Procedural Language
> Application Interface) + minor LRM maintence. Currently
> this draft is working its way through IEEE standardization.
>
>
> _VHDL + VHPI + VHDL-200X/VHDL-200X-FT + additional enhancements_
> At DAC 2006 the Accellera board approved an enhanced
> revision of 1076 that is VHDL + VHPI + enhancements.
> The IEEE VASG started the work in early 2003 as VHDL-200X.
> The Accellera VHDL Technical Subcommittee took over the
> work in 2005, funded its technical editing, and did
> super-human work to finalize it. In the near future
> an Accellera press release will announce this
> accomplishment.
>
> As an Accellera standard, this version is available
> for industry adoption - so let your vendors know you
> want it. In fact, the claim is that since Accellera
> standards are user driven, vendors are more willing to
> implement the standard features since they know the
> features are things desired and requested by users.
> This was demonstrated in the implementation of
> SystemVerilog (which started as an Accellera
> standard).
>
> I will be presenting a paper at Mentor's MARLUG on
> October 12th that details the changes. After that
> date the slides will be available at:
> http://www.synthworks.com/papers/
>
> Currently there are some older papers on that webpage
> that reflect the intent at the time they were written.
>
>
> _Accellera VHDL 2007_
> The Accellera VHDL TSC is continuing its work to
> enhance VHDL. Current items being worked on include
> constrained random, coverage, OO, interfaces, and
> verification data structures (associative arrays,
> memories, ...). When this work is completed, it
> will give VHDL similar verification capability to
> SystemVerilog.
>
>
> Join us and help create the next VHDL standards.
> Your support (either financial or participation or both)
> is greatly appreciated. For details see:
> http://www.eda-stds.org/vasg/#Participation
>
>
> By the way, if you have not checked the Accellera webpage
> recently, you will notice that VHDL is also listed
> prominently on the home page. See:
> http://www.accellera.org/home
>
>
> Best Regards,
> Jim Lewis
> IEEE VASG Chair
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
> Jim Lewis
> Director of Training (E-Mail Removed)
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL Training for Hardware Design and Verification
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~


Hi Jim,
Congraduation! Now you are chairman of the committee.

How about keyword "elsor" keyword?

At that time, you recommended me to contact a person who had the power
to do that while you were not in the committee. I didn't contacted the
person because I didn't like to do that: it would be beneficial to
every engineer in VHDL and Verilog circuit.

And last time we talked through the google about the introduction and
you nad many new ideas and we agured a lot, finally you asked me to
post most daunting design that used the technology and I posed the
design and after that I never heared your answer.

Thank you.

Weng

 
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David Ashley
Guest
Posts: n/a
 
      09-14-2006
Weng Tianxiang wrote:
> How about keyword "elsor" keyword?


How would you use it? I'm reminded of perl's "unless"
keyword .

-Dave

--
David Ashley http://www.xdr.com/dash
Embedded linux, device drivers, system architecture
 
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Jim Lewis
Guest
Posts: n/a
 
      09-14-2006
Weng,
What I remember is that for simple examples, elsor
works fine, however, for examples of the complexity
for which you posted it is very difficult if not
impossible to extract enough information to address your
issue.

On the other hand, an alternate consideration is to
have assertions that express mutual exclusion. For
example:

assert zero_one_hot(A_LE & B_LE & C_LE & D_LE)
report "%%%BUG: Mutual exclusion failed in design ..."
severity error ;


-- Looking forward and using new syntax introduced by
-- the Accellera VHDL 2006 revision
Reg4LeProc : process(Clk)
begin
if rising_edge(Clk) then
if A_LE then
Reg4Le <= A ;

elsif B_LE and AddrB ?= 15 then
Reg4LE <= B ;

elsif C_LE and AddrC ?= 14 then
Reg4LE <= C;

elsif D_LE then
Reg4Le <= D ;
end if ;
end if ;
end process ;


The alternate solution simplifies the expression of
the relationship between A_LE, B_LE, C_LE and D_LE.
It only requires a standardized function zero_one_hot
that is visible in the VHDL context. I will have to
do some searchin, but I think there is already something
like this in PSL (which was incorporated by reference -
however - I don't think the function is visible outside
of a PSL statement - yet).


So the steps to finializing the alternate solution are to
standardize a version of zero_one_hot (hopefully one that
is compatible with PSL) and revise 1076.6 to say vendors
should support this style of coding.


> Congratulation! Now you are chairman of the committee.

Yes, but I am chair of the group doing the administrative
work of making the revision a standard. The Accellera
VHDL TSC is doing all of the heavy lifting the next
revision (and perhaps more). In the Accellera group,
I am just an active member.


Cheers,
Jim


>
> Hi Jim,
> Congraduation! Now you are chairman of the committee.
>
> How about keyword "elsor" keyword?
>
> At that time, you recommended me to contact a person who had the power
> to do that while you were not in the committee. I didn't contacted the
> person because I didn't like to do that: it would be beneficial to
> every engineer in VHDL and Verilog circuit.
>
> And last time we talked through the google about the introduction and
> you nad many new ideas and we agured a lot, finally you asked me to
> post most daunting design that used the technology and I posed the
> design and after that I never heared your answer.
>
> Thank you.
>
> Weng
>



--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
 
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Amal
Guest
Posts: n/a
 
      09-15-2006
Jim Lewis wrote:
> As an Accellera standard, this version is available
> for industry adoption - so let your vendors know you
> want it.


I am already anxious for vendors to start implementing it. I just feel
that there has been a lot of support on the SystemVerilog side and
pushing it faster than VHDL.

Jim Lewis wrote:
> _Accellera VHDL 2007_
> The Accellera VHDL TSC is continuing its work to
> enhance VHDL. Current items being worked on include
> constrained random, coverage, OO, interfaces, and
> verification data structures (associative arrays,
> memories, ...). When this work is completed, it
> will give VHDL similar verification capability to
> SystemVerilog.
>


SystemVerilog brought most features already available to VHDL to
Verilog users and a lot more with support of vendors and the industry.
As a VHDL user, I just feel left behind and overwhelmed with the amount
of support for SystemVerilog and I feel that the activities on the VHDL
front have been very slow compared to SystemVerilog.

Although I thank everyone involved for completing the standard and I
hope that vendor support is coming sooner than later.
-- Amal

 
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Jim Lewis
Guest
Posts: n/a
 
      09-15-2006
Amal,
>>As an Accellera standard, this version is available
>>for industry adoption - so let your vendors know you
>>want it.

>
>
> I am already anxious for vendors to start implementing it. I just feel
> that there has been a lot of support on the SystemVerilog side and
> pushing it faster than VHDL.


For a vendor, implementing anything is a business investment.
The more interest they get from their users, the more quickly
they will implement it.

The claim for rapid implementation of SystemVerilog is that
it was a user driven standard. This VHDL effort followed the
same process, so it should enjoy the same rapid implementation.


>>_Accellera VHDL 2007_
>>The Accellera VHDL TSC is continuing its work to
>>enhance VHDL. Current items being worked on include
>>constrained random, coverage, OO, interfaces, and
>>verification data structures (associative arrays,
>>memories, ...). When this work is completed, it
>>will give VHDL similar verification capability to
>>SystemVerilog.
>>

>
>
> SystemVerilog brought most features already available to VHDL to
> Verilog users and a lot more with support of vendors and the industry.
> As a VHDL user, I just feel left behind and overwhelmed with the amount
> of support for SystemVerilog and I feel that the activities on the VHDL
> front have been very slow compared to SystemVerilog.


Some of that is marketing propaganda. Some vendors just recently
implemented the OO features of SystemVerilog. The challenge for
the Accellera VHDL TSC will be to have the OO, constrained random,
interfaces, ... features for DAC 07.

> Although I thank everyone involved for completing the standard and I
> hope that vendor support is coming sooner than later.

Me too. Given that it is Accellera uses user driven process,
there is no reason why vendors would not already be working on it.
However, compell them further by letting them know your interest
in the standard.

Going further, it would also be helpful to get additional
organizations to join Accellera and help fund the effort.
See http://www.accellera.org/activities/vhdl/

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
 
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Amal
Guest
Posts: n/a
 
      09-15-2006
Jim Lewis wrote:
>
> The challenge for the Accellera VHDL TSC will be to
> have the OO, constrained random, interfaces, ...
> features for DAC 07.
>


Do you have any insight or documents for public view on these subjects,
especially OO?

Jim Lewis wrote:
> Going further, it would also be helpful to get additional
> organizations to join Accellera and help fund the effort.
> See http://www.accellera.org/activities/vhdl/
>


How can individual VHDL users help?

-- Amal

 
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Jim Lewis
Guest
Posts: n/a
 
      09-15-2006
Amal


>>The challenge for the Accellera VHDL TSC will be to
>>have the OO, constrained random, interfaces, ...
>>features for DAC 07.
>>

>
>
> Do you have any insight or documents for public view on these subjects,
> especially OO?

Too soon yet.


>>Going further, it would also be helpful to get additional
>>organizations to join Accellera and help fund the effort.
>>See http://www.accellera.org/activities/vhdl/
>>

>
>
> How can individual VHDL users help?

Join Accellera - even as a non-member. Participate
in the VHDL subgroups - particularly the requirements
group. This helps determine what is important to users.

The other groups require more experience, but if you have
it and you can contribute to writing details of enhancements or
LRM modifications. Generally things go best when someone
with a vested interest in a proposal works on it.

Best Regards,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
 
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Hans
Guest
Posts: n/a
 
      09-17-2006

"Amal" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ups.com...
> Jim Lewis wrote:
>> As an Accellera standard, this version is available
>> for industry adoption - so let your vendors know you
>> want it.

>
> I am already anxious for vendors to start implementing it. I just feel
> that there has been a lot of support on the SystemVerilog side and
> pushing it faster than VHDL.


That is not because of the language itself but simply because
SystemVerilog/SystemC support essential verification methodologies like
Transaction Level Modelling, Constraint Random Verification and Functional
Coverage. There is absolutely no reason to abandon VHDL since it is still a
very capable RTL language. However, if you have to develop an all singing
all dancing testbench or you want to do some behaviour modelling of your
system you definitely don't want to use VHDL/Verilog but instead use a
language that support the above techniques.

It is also true that most EDA tools (at least Modelsim) can mix these
languages at any level of the hierarchy seamlessly without you having to
worry about any interface issues. Thus you can use VHDL for your DUT and say
SystemC for your testbench and SVA for your assertions.

It is questionable if the EDA industry needs an OO-VHDL given that
SystemC/SystemVerilog can be used so effectively with VHDL and have already
such a headstart. However, what is very cool of the VHDL-2006 standard is
the inclusion of PSL. This is IMHO the best addition to the language and can
make a serious impact on the quality of your verification (assuming you use
it properly , the only stumble block which is seriously hampering the
uptake of this language is the high price EDA vendors are charging for it.

Hans
www.ht-lab.com


>
> Jim Lewis wrote:
>> _Accellera VHDL 2007_
>> The Accellera VHDL TSC is continuing its work to
>> enhance VHDL. Current items being worked on include
>> constrained random, coverage, OO, interfaces, and
>> verification data structures (associative arrays,
>> memories, ...). When this work is completed, it
>> will give VHDL similar verification capability to
>> SystemVerilog.
>>

>
> SystemVerilog brought most features already available to VHDL to
> Verilog users and a lot more with support of vendors and the industry.
> As a VHDL user, I just feel left behind and overwhelmed with the amount
> of support for SystemVerilog and I feel that the activities on the VHDL
> front have been very slow compared to SystemVerilog.
>
> Although I thank everyone involved for completing the standard and I
> hope that vendor support is coming sooner than later.
> -- Amal
>



 
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