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VHDL - Calling a JK flipflop through a procedure

 
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Old 09-13-2006, 07:01 AM   #1
Unhappy Calling a JK flipflop through a procedure


I am getting an uninitialized (U) Q and Qnot when I call a procedure that describes a JK flipflop wih both inputs to be the same:

library ieee;
use ieee.std_logic_1164.all;

entity UpDownCounter is
port(CLK : std_logic;
J, K : in std_logic;
Qo, QNOTo, J1orK1, UP, DOWNin : inout std_logic;
QoUP, QNOToDOWN, DOWN : inout std_logic;
Q_1, QNOT_1 : inout std_logic);
end UpDownCounter;

architecture UpDownCounterProcedure of UpDownCounter is
--This procedure describes a two-input AND gate with zero delay
procedure and2 (Ap, Bp : in std_logic; Cp : out std_logic) is
begin
if Ap = '1' and Bp = '1'
then Cp := '1';
else Cp := '0';
end if;
end procedure and2;

--This procedure describes a two-input OR gate with zero delay
procedure or2 (Ap, Bp : in std_logic; Cp : out std_logic) is
variable Cp_temp : std_logic;
begin
if Ap = '0' and Bp = '0'
then Cp_temp := '0';
else Cp_temp := '1';
end if;
Cp := Cp_temp;
end procedure or2;

--This procedure describes a JK flipflop
procedure jkff (Jp, Kp : in std_logic; Qp, QNOTp : inout std_logic) is

variable Qp_temp, QNOTp_temp : std_logic;
begin
if Jp = '1' and Kp = '0'
then Qp_temp := '1';
elsif Jp = '0' and Kp = '1'
then Qp_temp := '0';
elsif Jp = '0' and Kp = '0'
then Qp_temp := Qp;
else Qp_temp := not Qp;
end if;

Qp := Qp_temp;
QNOTp_temp := not Qp_temp;
QNOTp := QNOTp_temp;
end procedure jkff;

--this procedure describes an inverter
procedure inv (DOWNp : in std_logic; variable DOWNp_out : inout std_logic) is
begin
if DOWNp = '0'
then DOWNp_out := '1';
else DOWNp_out := '0';
end if ;
end procedure inv;

begin

counter : process (J, K, UP, DOWNin, CLK)
variable DOWNout, QoUPout, QNOToDOWNout, Qout, QNOTout : std_logic;
variable Qout_1, QNOTout_1 : std_logic;
variable J1orK1out, K1 : std_logic;

begin
if rising_edge(CLK) then
--calling to the procedure JKflipflop for FF0
jkff (J, K, Qout, QNOTout); -- working properly
Qo <= Qout;
QNOTo <= QNOTout;

--calling inverter procedure
inv (DOWNin, DOWNout);
DOWN <= DOWNout;

-- calling two and gates through procedure and2
and2 (Qout, UP, QoUPout);
QoUP <= QoUPout;
and2 (DOWNout, QNOTout, QNOToDOWNout);
QNOToDOWN <= QNOToDOWNout;

-- calling or2 procedure
or2 (QNOToDOWNout, QoUPout, J1orK1out);
J1orK1 <= J1orK1out;

--THIS IS WHERE I GET IN TROUBLE
-- calling procedure JKfliflop for FF1
jkff(J1orK1out, J1orK1out, Qout_1, QNOTout_1); --same inputs give me problem

--Qout_1 and QNOT_1 get a value of 'U' all thru the simulation
--please tell me what I am doing wrong, and how I can fix it.
--Thanks
--Willie


end if;
end process counter;
end UpDownCounterProcedure;


willie

Last edited by willie : 09-13-2006 at 10:30 PM.
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