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SPI confusion

 
 
Niv
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      09-12-2006
I have to interface several DACs, ADCs and temp sensors (all different
mnfrs of course) to an FPGA.
Now, the data sheets all say they are SPI compatible.
All seem to have a serial clock and chip select input.
The DACs have serial data input,
the ADCs have serial data output,
the temp sensor has a single data I/O pin!

Now the SPI spec seems to sort of agree (not with single I/O pin
though).
I need to write some VHDL that'll handle all the above, so I have a
common module,
in, out & I/O controlled by generics probably (as well as max clock
speed).

The VHDL block will be the master, controlled via our in-house common
bus structure from
a remote(ish) processor

Anyone point me at some SPI clarification please?

(Or I could be greedy & ask for pre-written example to start me off).

Regards, Niv.

 
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Paul Uiterlinden
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      09-12-2006
Niv wrote:

> Anyone point me at some SPI clarification please?


I think http://en.wikipedia.org/wiki/Serial_..._Interface_Bus
is a good starting point. See also the external links.

--
Paul.

 
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David R Brooks
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      09-13-2006
Niv wrote:
> I have to interface several DACs, ADCs and temp sensors (all different
> mnfrs of course) to an FPGA.
> Now, the data sheets all say they are SPI compatible.
> All seem to have a serial clock and chip select input.
> The DACs have serial data input,
> the ADCs have serial data output,
> the temp sensor has a single data I/O pin!
>
> Now the SPI spec seems to sort of agree (not with single I/O pin
> though).
> I need to write some VHDL that'll handle all the above, so I have a
> common module,
> in, out & I/O controlled by generics probably (as well as max clock
> speed).
>
> The VHDL block will be the master, controlled via our in-house common
> bus structure from
> a remote(ish) processor
>
> Anyone point me at some SPI clarification please?
>
> (Or I could be greedy & ask for pre-written example to start me off).
>
> Regards, Niv.
>

The temp sensor isn't a Dallas "One Wire" device, by any chance?
1W and SPI are two very different beasts.
 
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Niv
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      09-13-2006

David R Brooks wrote:
> Niv wrote:
> > I have to interface several DACs, ADCs and temp sensors (all different
> > mnfrs of course) to an FPGA.
> > Now, the data sheets all say they are SPI compatible.
> > All seem to have a serial clock and chip select input.
> > The DACs have serial data input,
> > the ADCs have serial data output,
> > the temp sensor has a single data I/O pin!
> >
> > Now the SPI spec seems to sort of agree (not with single I/O pin
> > though).
> > I need to write some VHDL that'll handle all the above, so I have a
> > common module,
> > in, out & I/O controlled by generics probably (as well as max clock
> > speed).
> >
> > The VHDL block will be the master, controlled via our in-house common
> > bus structure from
> > a remote(ish) processor
> >
> > Anyone point me at some SPI clarification please?
> >
> > (Or I could be greedy & ask for pre-written example to start me off).
> >
> > Regards, Niv.
> >

> The temp sensor isn't a Dallas "One Wire" device, by any chance?
> 1W and SPI are two very different beasts.


No, it's an LM70, supposedly "SPI" but has a single I/O pin along with
clock & cs pins.
It switches from output to input after 16 clocks if cs is still active.
Think I'll just not use that feature as it powers up in "normal" mode.

Niv.

 
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devices
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      09-13-2006
I guess that "SPI compatible" only refers to
"One master device - to - One slave device" topology.
Chances are that they were not meant to be used in a chain

"Niv" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
>
> David R Brooks wrote:
> > Niv wrote:
> > > I have to interface several DACs, ADCs and temp sensors (all different
> > > mnfrs of course) to an FPGA.
> > > Now, the data sheets all say they are SPI compatible.
> > > All seem to have a serial clock and chip select input.
> > > The DACs have serial data input,
> > > the ADCs have serial data output,
> > > the temp sensor has a single data I/O pin!
> > >
> > > Now the SPI spec seems to sort of agree (not with single I/O pin
> > > though).
> > > I need to write some VHDL that'll handle all the above, so I have a
> > > common module,
> > > in, out & I/O controlled by generics probably (as well as max clock
> > > speed).
> > >
> > > The VHDL block will be the master, controlled via our in-house common
> > > bus structure from
> > > a remote(ish) processor
> > >
> > > Anyone point me at some SPI clarification please?
> > >
> > > (Or I could be greedy & ask for pre-written example to start me off).
> > >
> > > Regards, Niv.
> > >

> > The temp sensor isn't a Dallas "One Wire" device, by any chance?
> > 1W and SPI are two very different beasts.

>
> No, it's an LM70, supposedly "SPI" but has a single I/O pin along with
> clock & cs pins.
> It switches from output to input after 16 clocks if cs is still active.
> Think I'll just not use that feature as it powers up in "normal" mode.
>
> Niv.
>



 
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Dal
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      09-14-2006
Downalod the Motorola (Freescale) 68HC11 data sheet and see the
Synchronous Peripheral Interface section.

Darrin

Niv wrote:
> I have to interface several DACs, ADCs and temp sensors (all different
> mnfrs of course) to an FPGA.
> Now, the data sheets all say they are SPI compatible.
> All seem to have a serial clock and chip select input.
> The DACs have serial data input,
> the ADCs have serial data output,
> the temp sensor has a single data I/O pin!
>
> Now the SPI spec seems to sort of agree (not with single I/O pin
> though).
> I need to write some VHDL that'll handle all the above, so I have a
> common module,
> in, out & I/O controlled by generics probably (as well as max clock
> speed).
>
> The VHDL block will be the master, controlled via our in-house common
> bus structure from
> a remote(ish) processor
>
> Anyone point me at some SPI clarification please?
>
> (Or I could be greedy & ask for pre-written example to start me off).
>
> Regards, Niv.


 
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