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VHDL - signals in Procedure

 
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Old 09-12-2006, 06:32 AM   #1
Default signals in Procedure


Hi all,

Here is a syntex for procedure declaration:

-----------------
procedure my_proc (parameter_interface_list)
{subprogram declarative part}
begin
{sequential statement}
end procedure;
-----------------
Where are signals defined in procedure ? (These signals are used for
implementing pipelining)

For example how will below signal be defined in procedure ?
if I decleare it in (parameter_interface_list) as

SIGNAL dat1s0: std_logic_vector(15 DOWNTO 0);
than it is assumed to be as input and I can't do something
like this
dat1s0 <= in1;
Where in1 is the input .

All the examples in books use variables in {subprogram declarative
part} .
So ambiguity remains in my mind regarding usuage of intermediate
signals in procedure.

Am I clear with my question ?
Should I paste my codes ?

Regards
Ved



Ved
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Old 09-12-2006, 08:59 AM   #2
Paul Uiterlinden
 
Posts: n/a
Default Re: signals in Procedure

Ved wrote:

> Hi all,
>
> Here is a syntex for procedure declaration:
>
> -----------------
> procedure my_proc (parameter_interface_list)
> {subprogram declarative part}
> begin
> {sequential statement}
> end procedure;
> -----------------
> Where are signals defined in procedure ? (These signals are used
> for implementing pipelining)


You can't declare signals in a procedure.

You can have parameters declared as signals though. The signals they
are associated with (connected to) are declared in the architecture.

--
Paul.

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Old 09-12-2006, 01:59 PM   #3
Andy
 
Posts: n/a
Default Re: signals in Procedure

You cannot declare signals inside a procedure, but if the procedure is
defined inside a process, then it has visibility and can assign to any
signal that is visible to the process.

When you say you need pipelining in the procedure, remember that most
synthesis tools do not accept subprograms (functions or procedures)
with wait statements. Therefore the entire procedure has to operate in
one clock. If it is called once every clock then it can implement
pipelining.

Variables can also imply registers if they are read before being
written during a clock cycle execution, forcing them to "remember" the
value from the last clock. Note that variables declared internally to
the procedure have no "memory" from one execution of the procedure to
the next, and therefore cannot be used for registers. Variables
declared before the procedure in the same process do. They can either
be accessed directly, or passed as inout parameters to the procedure.

Andy


Paul Uiterlinden wrote:
> Ved wrote:
>
> > Hi all,
> >
> > Here is a syntex for procedure declaration:
> >
> > -----------------
> > procedure my_proc (parameter_interface_list)
> > {subprogram declarative part}
> > begin
> > {sequential statement}
> > end procedure;
> > -----------------
> > Where are signals defined in procedure ? (These signals are used
> > for implementing pipelining)

>
> You can't declare signals in a procedure.
>
> You can have parameters declared as signals though. The signals they
> are associated with (connected to) are declared in the architecture.
>
> --
> Paul.


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