I'm having in trying to learn VHDL coding for use with XiLinx ISE WebPack.
I'm obviously new to VHDL but I understand the basics of VHDL for single entities, components and architecture. But it seems from all the examples that I look at that all the inputs and output are treated as external port signals. I'm having trouble seeing how one integrates two or more entities and how one distinguishes external port (chip) signals vs internal signals that don't come to the external chip. I'm having specifically two problems.
How to integrate two or more seperate entities (or components, if my terminology is incorrect) into an overall project. If I have multiple functions, as explained in my example, how is that done?
How to specify which signals are internal vs signals that are external chip pins
I have created a simple example that has two components (entities). One is an ADDER and the other is a DECODER. Nevermind, that this might be able to be done with a single entity. And nevermind this is a sill example. I'm not looking for a way to do this in one component or entity. I want to see an example with this done as two entities (or 2 components). I have specified and the rules of operation (NOT a better way of doing it, in one component). This will show me an example of integrating two entities (or components) and how to specify which signals are external and which are internal.
The block diagram, showing the ADDER and DECODER functional blocks are shown here:
First question: Is the ADDER and DECODER referred to as components, while the overall design might be the entity? What exactly is the difference between an entity and a component? Both seem similar.
Operation (in this sequence):
Basic example operation: The controller will setup A and B and raise "Mode" signal for only 1 Clk rising edge and then remove "Mode" signal.
Then on the next 4 Clk signals, X will pump out something based on the decode. It is irrlevant what the decode is but for argument sake, say that the 4 outputs are
The Value of C,
The Sum of bits of C,
00 if C is even or 11 if C is odd, and
a canned output of 11.
Some more details
There will be a total of 5 clock cycles that I'm concerned about in this example
On rising edge of Clk 1, Mode will be 1 and C will = A + B
On falling edge of clock 1, Mode will be 0 and C will stil be latched
On the rising edge of Clk 2, X will be C
On the rising edge of Clk 3, X will be the sum of bits in C
On the rising edge of Clk 4, X will be 00 if C was even or 11 if C was odd 7
On the rising edge of Clk 5, X will be a canned output of 11
A = 1
B = 2
C = 3
X = 3, 2, 1, 3
This is just an example and not a real application. This seems like something that is quite easy but for someone who is just learning this, it's not so trivial. Can someone show me what the framework (definitions of entity, components, processes, state machine, if any, etc) of the VHDL file, might look like, for this specific example, the way I have described it? Again, I'm not looking for simplification or a better way of doing it. This is an exercize to learn the proper way to implement multiple components in a design and specify internal vs. external signals.