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Xilinx ISE Synthesize of ROM

 
 
Benjamin Todd
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      09-06-2006
Ah, thanks for that. I guess provided your coefficients are compatible with
the two halves then it makes sense to share them.
<(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
> Brian Drummond schrieb:
>
>> On Wed, 6 Sep 2006 11:27:50 +0200, "Benjamin Todd"
>> <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPIT ALS.ch> wrote:
>>
>> >Excellent - I'm pleased you managed, but one quick question - how come
>> >you
>> >need a dual-port ROM? I figure dual port is good for read /write... but
>> >read
>> >/ read? Interesting.

>>
>> It's a good technique for doubling the number of read ports (e.g. for
>> filter coefficients) available. If you need small ROMs the two ports can
>> act as completely independent ROMs mapped into different areas within
>> the same BlockRam.

>
> That's why I need them. I have 180 arrays consisting of 13 17-Bit
> values. But there are only 136 BRAMs on my board. So I just "half" them
> and I've now theoretically space for 272 of my Arrays.
>
> The Dual Port BRAM can be designed be using a dual port BRAM and just
> set the we input constantly to zero (if active high).
>
> Regards,
> Peter
>
>>
>> - Brian

>



 
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Benjamin Todd
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      09-06-2006
"Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPIT ALS.ch>
wrote in message news:edmetg$cd5$(E-Mail Removed)...
> Ah, thanks for that. I guess provided your coefficients are compatible
> with the two halves then it makes sense to share them.


or indeed making more effective use of the blockram, even if the
coefficients aren't shared

> <(E-Mail Removed)> wrote in message
> news:(E-Mail Removed) oups.com...
>> Brian Drummond schrieb:
>>
>>> On Wed, 6 Sep 2006 11:27:50 +0200, "Benjamin Todd"
>>> <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPIT ALS.ch> wrote:
>>>
>>> >Excellent - I'm pleased you managed, but one quick question - how come
>>> >you
>>> >need a dual-port ROM? I figure dual port is good for read /write... but
>>> >read
>>> >/ read? Interesting.
>>>
>>> It's a good technique for doubling the number of read ports (e.g. for
>>> filter coefficients) available. If you need small ROMs the two ports can
>>> act as completely independent ROMs mapped into different areas within
>>> the same BlockRam.

>>
>> That's why I need them. I have 180 arrays consisting of 13 17-Bit
>> values. But there are only 136 BRAMs on my board. So I just "half" them
>> and I've now theoretically space for 272 of my Arrays.
>>
>> The Dual Port BRAM can be designed be using a dual port BRAM and just
>> set the we input constantly to zero (if active high).
>>
>> Regards,
>> Peter
>>
>>>
>>> - Brian

>>

>
>



 
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KJ
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      09-07-2006

"Brian Drummond" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> On Wed, 6 Sep 2006 11:27:50 +0200, "Benjamin Todd"
> <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPIT ALS.ch> wrote:
>
>>Excellent - I'm pleased you managed, but one quick question - how come
>>you
>>need a dual-port ROM? I figure dual port is good for read /write... but
>>read
>>/ read? Interesting.

>
> It's a good technique for doubling the number of read ports (e.g. for
> filter coefficients) available. If you need small ROMs the two ports can
> act as completely independent ROMs mapped into different areas within
> the same BlockRam.
>


Are you assuming that the Xilinx software doesn't have enough smarts to
combine several small ROMs into a single BlockRam? Or is this a known
limitation that you just have to code around (i..e by making a single dual
port ROM when what your design intended was two smaller ROMs).

In other words, if you had simply coded the "180 arrays consisting of..."
(as you mentioned in a later post) as being 180 single port ROMs the fitter
'should' be able to partition the BlockRam usage to fit them all into the
136 that are available. The 'Brand A' software seems to do a good job of
parsing things into available memory of different sizes, so I'm wondering
why the 'Brand X' software wouldn't as well....unless like I said, you're
making an assumption that isn't necessary or desirable.

Where is Peter Alfke when you need him?

KJ


 
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peter.kampmann@googlemail.com
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      09-08-2006

KJ schrieb:

> Are you assuming that the Xilinx software doesn't have enough smarts to
> combine several small ROMs into a single BlockRam? Or is this a known
> limitation that you just have to code around (i..e by making a single dual
> port ROM when what your design intended was two smaller ROMs).


Well, I'm not assuming it I made the experience that this does not
fit
First, I implemented the 180 array consisting of, the "brand X"
Software recognizes that
I want to instantiate ROMs but they were mapped into LUTs.
Of course, it is possible that the software will map single port roms
into a dual port block rom, I have not tried it.

Regards,
Peter

> In other words, if you had simply coded the "180 arrays consisting of..."
> (as you mentioned in a later post) as being 180 single port ROMs the fitter
> 'should' be able to partition the BlockRam usage to fit them all into the
> 136 that are available. The 'Brand A' software seems to do a good job of
> parsing things into available memory of different sizes, so I'm wondering
> why the 'Brand X' software wouldn't as well....unless like I said, you're
> making an assumption that isn't necessary or desirable.
>
> Where is Peter Alfke when you need him?
>
> KJ


 
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