Are these coefficients going to be used as inputs for a testbench, or used in a synthesized design, eg, stored in ROM or RAM?
I've got a project that uses MATLAB and VHDL a great deal, and I don't know if it is the best method of passing info between the two but I have a way that works.
For testbenches, everything is encoded as hex, but stored as text, eg, the number 123 would be the string "0000007B" (For 32 bit words). The VHDL testbench uses the std.textio package to read each line, and I've written procedures to convert from string to std_logic_vectors.
For RAM/ROM you can write out a .coe file and use the Xilinx Core Generator to generate RAM/ROM with corresponding initial values. I've found it generates a .mif file (another text file) which I believe is the file read by the simulator/synthesizer. Instead of re creating the RAM/ROM everytime with a new .coe file, perhaps you could alter the .mif directly.
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