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| Thread | Thread Starter | Forum | Replies | Last Post |
| What to do when post-synthesis simulation do not pass | jasonL | VHDL | 2 | 06-04-2007 02:22 PM |
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| Difference between Functional and Post-Synthesis Simulation | Peppe | VHDL | 3 | 09-10-2006 11:43 PM |
| SOS! newbie question about synthesizable VHDL : synthesis run successfully but post-synthesis failed... | walala | VHDL | 4 | 09-09-2003 08:41 AM |
| what are the possible reasons that successful pre-synthesis simulation + successful synthesis = failed post-synthes | walala | VHDL | 4 | 09-08-2003 01:51 PM |