Global signal conservation

Hi,

In opencores DDR implementation, the author uses a PLL
to generate a clock of multiple phases. The PLL outputs
true and inverted signals, in perfect sync.

However the author doesn't use the inverting output of
the PLL -- to generate an inverted output he inverts the
true clock output and uses that.

I'm trying to figure out why he did this. Is it because if
you use the single clock source, then you only need one
global clock buffer -- but if you use both, presumably
there would be 2 global clock buffers used, and this
is excessive for the design?

Moreover the design needs a 2 phased clock. All clocks
are 100 mhz. So 2 phases, 2 types (true/inverted) with
minimum clock skew would necessitate 4 global clock
buffers, right?

Instead evidently he opted for just the 2 true clocks,
then uses inverters when he wants the inverted version.

Now this means the inverted signal will be delayed by
the inverter. This appears on the order of .5 to 1 ns in
the parts I'm interested in.

So perhaps it's a tradeoff -- minimum skew requires
4 global clock buffers. Perhaps the inverter approach
conserves global clock buffers at the expense of a little
bit of skew.

Anyway I just am looking for a sanity check. Does the
reasoning above sound...reasonable? When designing
is it necessary to keep these things in mind?

Thanks--
Dave

David Ashley

I don't know what technology your example is using, but for Xilinx Virtex
devices (and I believe also the old 4k), inverters are generally 'free': no
logic resource penalty, and no timing delay penalty. I suspect Altera and
the other vendors do something comparable:

N-input LUTs - inverter is free, it just changes the contents of the LUT
clock inputs to FFs - true & complement are generally available.

I believe that in the past, some constructs (FFs in IOBs?) did not support
'free inversion', but I think most do nowadays.

Now, for high-speed designs in Virtex 2 & Virtex 2 Pro, where there is a
significant concern about duty cycle symmetry, the DCMs provide true and
complement clocks--this requires 2 BUFGs. However, Xilinx has App notes
showing how to use a Macro to use just the single BUFG--do a search on
'local clock inversion.' We have used it successfully on Virtex 2 Pro
devices at well over 600 MHz DDR. (This wasn't a DDR memory interface,
which would have different timing parameters than our custom interface.)

I would expect the newer Xilinx and Altera parts to be able to achieve
higher performance.

JTW

"David Ashley" <> wrote in message
news:44ec9bab$...
> Hi,
>
> In opencores DDR implementation, the author uses a PLL
> to generate a clock of multiple phases. The PLL outputs
> true and inverted signals, in perfect sync.
>
> However the author doesn't use the inverting output of
> the PLL -- to generate an inverted output he inverts the
> true clock output and uses that.
>
> I'm trying to figure out why he did this. Is it because if
> you use the single clock source, then you only need one
> global clock buffer -- but if you use both, presumably
> there would be 2 global clock buffers used, and this
> is excessive for the design?
>
> Moreover the design needs a 2 phased clock. All clocks
> are 100 mhz. So 2 phases, 2 types (true/inverted) with
> minimum clock skew would necessitate 4 global clock
> buffers, right?
>
> Instead evidently he opted for just the 2 true clocks,
> then uses inverters when he wants the inverted version.
>
> Now this means the inverted signal will be delayed by
> the inverter. This appears on the order of .5 to 1 ns in
> the parts I'm interested in.
>
> So perhaps it's a tradeoff -- minimum skew requires
> 4 global clock buffers. Perhaps the inverter approach
> conserves global clock buffers at the expense of a little
> bit of skew.
>
> Anyway I just am looking for a sanity check. Does the
> reasoning above sound...reasonable? When designing
> is it necessary to keep these things in mind?
>
> Thanks--
> Dave
>

jtw