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VHDL - No clock signals found in design... |
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08-22-2006, 12:26 AM
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#1 |
No clock signals found in design...
Whenever i synthesize i top level block in xilinx, i get this msg, "No clock signals found in design", so i dont get information about the clock speed or clock delay; this is wierd since i have a central clk signal that drives a lot of Flip flops
how do i correct this in synthesis? how do i make xilinx realize i have a clk sig that needs to be treated appropriately? i have no IBUFs, or CLKBufs in design Jerrie85 |
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08-24-2006, 05:42 AM
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#2 |
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Junior Member
Join Date: Aug 2006
Posts: 7
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i'm sure someone's got this before...does anyone know? pleasee help
Jerrie85 |
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08-24-2006, 05:42 AM
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#3 |
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Junior Member
Join Date: Aug 2006
Posts: 7
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i'm sure someone's got this before...does anyone know? pleasee help
Jerrie85 |
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