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VHDL - Timing Simulation - (ModelSim) |
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HI.
Well this FAQ has been very kind to me and wish it to be the same for all learners. What my main prob is, i want to learn "TIMING SIMULATION". I'am basically a Front end VErification engineer, i have no idea on Timing Simulation. SUppose i have a simple design in VHDL. say a counter. i have done the functionality simulation and now want to try out the timing simualtion. i was told timing sim. is only for designers and not for verification engineers. But i want to get some idea may never know when it will be help full. I just tried out the timing simulation run and i found out that i need to add few libraries and few files. (guess the library files are for ModelSim) i have no idea what i'am supposed to do or what files and libraries i need to add in order to get the simulation. I'am using Xilinx editor and ModelSim Simulation tool. could anyone out here plz tell me, how to generate a file from modelsim after functionality simulation and what kind of files to add.it will be really helpfull. Thanks and lots. CHEERS!! Abs |
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