inc2modL architecture

I need help, please, for write a simple architecture.

The entity for this architecture is:

entity inc2modL is
port ( entrada : in std_logic_vector(7 downto 0);
modulo : in std_logic_vector(7 downto 0);
reset : in std_logic;
clock : in std_logic;
salida : out std_logic_vector(7 downto 0)
);
end inc2modL;

the objective of this entity is:

salida = (entrada + 2) mod (modulo)


Anybody can help me?.

Thanks

Loppy

Loppy ha escrito:

> I need help, please, for write a simple architecture.
>
> The entity for this architecture is:
>
> entity inc2modL is
> port ( entrada : in std_logic_vector(7 downto 0);
> modulo : in std_logic_vector(7 downto 0);
> reset : in std_logic;
> clock : in std_logic;
> salida : out std_logic_vector(7 downto 0)
> );
> end inc2modL;
>
> the objective of this entity is:
>
> salida = (entrada + 2) mod (modulo)
>
>

sorry,

mod is the rest of a division.

for example:

entrada := "00000111";
modulo := "00000100";

salida will be "00000001"

> Anybody can help me?.
>
> Thanks

Loppy