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VHDL - false edge detection

 
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Old 08-18-2006, 07:10 AM   #1
Default false edge detection


Hi everyone,

Can someone please tell me how do I detect a false edge(glitch) in a
clock signal?
Any pulse with a pulse width considerablys shorter than the normal
clock is considered as a false edge(glitch).

Thanks in advance..
Apurva



apurva
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Old 08-18-2006, 04:52 PM   #2
Jerry Avins
 
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Default Re: false edge detection
apurva wrote:
> Hi everyone,
>
> Can someone please tell me how do I detect a false edge(glitch) in a
> clock signal?
> Any pulse with a pulse width considerablys shorter than the normal
> clock is considered as a false edge(glitch).



Is this a software question, or hardware? There are good solutions for
specific problems, but there is no all-purpose solution.

Jerry
--
Engineering is the art of making what you want from things you can get.
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Jerry Avins
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