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VHDL - Cast natural to std_logic_vector (and the other way) |
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08-14-2006, 10:33 PM
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#1 |
Cast natural to std_logic_vector (and the other way)
Hi,
Is it possible to convert a variable of type natural to a std_logic_vector (and do the opposite). I am trying to do this and either I am not using the correct commands or the wrong library. Does anyone know how to do this? I have used an integer instead but would like to know if it is possible. Many Thanks badwolf500 |
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