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VHDL - comparing frequency of two clocks |
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Hi Everyone,
Does anyone have any idea of how to compare two reference clocks using completely digital logic .The problem is something like this There are two slow ref clocks (Khz) CLKA (rc clock) CLKB (crystal clock) and a fast sys_clk (pll clock) Mhz range If freq CLKA > freq CLKB then op1 = 1; elsif freq CLKA < freq CLKB op2 = 1 else op3 = 1; end if; Eagerly awaiting some solutions arant |
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