Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Character Map with Xilinx FPGA

Reply
Thread Tools

Character Map with Xilinx FPGA

 
 
usenet
Guest
Posts: n/a
 
      07-22-2006
Hello,

I'm trying to display text via the vga port of my xilinx spartan-3. The
question is how do I do it. I now that I have to generate a character-map or
a character rom. But has some one experience with this, i.e. some vhdl code,
and how do I do this with modelsim.

I already searched with google and either I'm too dumb or there is nothing
helpful out there. So how do I code the characters into vhdl with modelsim
so that it will be synthesized on a spartan-3. Has someone a coding example?

Thanks in advance


 
Reply With Quote
 
 
 
 
Martin Thompson
Guest
Posts: n/a
 
      07-24-2006
"usenet" <(E-Mail Removed)> writes:

> Hello,
>
> I'm trying to display text via the vga port of my xilinx spartan-3. The
> question is how do I do it. I now that I have to generate a character-map or
> a character rom. But has some one experience with this, i.e. some vhdl code,
> and how do I do this with modelsim.
>


Do you have the bitmaps you want to use?
Assuming they are simple 8 bit wide characters with the same number of
rows (let's say 8 for this exambple) in each you can do:
constant char_rom : integer range 0 to 255 := (
0,0,0,0,0,0,0,0, -- space char
<<<row 1 of !>>>, <<<row 2 of !>>>, etc for !
<<<row 1 of ">>>, <<<row 2 of ">>>, etc for "
etc for whole of ASCII set
);


Then if you want the values for the character in signal c:
char_rom(c-character'pos(' ')) is the first row
char_rom(c-character'pos(' ')+1) is the second row

[Ahh, the days of defining user defined characters on the Beeb with VDU
commands come flooding back ]

HTH!

Martin

--
http://www.velocityreviews.com/forums/(E-Mail Removed)
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt

 
Reply With Quote
 
 
 
 
usenet
Guest
Posts: n/a
 
      07-26-2006
Thanks for the answer but I solved it on my own. Anyway, I will post it
here:

signal addr : std_logic_VECTOR(8 downto 0);

type ram_t is array (0 to 511) of std_logic_vector(7 downto 0);

-- place characters inside the ram. Each letter consists of 8 rows.

signal ram : ram_t :=

(

"00111100",

"01100110",

..

..

..

"00000000"

);

..

..

..

-- read the ram and display it to dout

dout <= ram(conv_integer(addr));





Have I nice day

Da Unseen


 
Reply With Quote
 
Martin Thompson
Guest
Posts: n/a
 
      07-26-2006
"usenet" <(E-Mail Removed)> writes:

> Thanks for the answer but I solved it on my own. Anyway, I will post it
> here:
>


Excellent!
<snip>
>
> dout <= ram(conv_integer(addr));
>


This looks like some std_logic_arith... this is a very out-of-date
coding style, you should be using ieee.numeric_std these days as it's
a proper standard and better behaved than the Synopsys libraries that
they (inexplicably) compiled into the ieee lib.

See the VHDL FAQ for the detailed reasons why.

Cheers,
Martin

--
(E-Mail Removed)
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt

 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
asynchronous counter an Xilinx FPGA for a newbie Georges Konstantinidis VHDL 12 08-04-2006 04:42 AM
Designing MUX with tri sate buffers in xilinx virtex II FPGA Oleg VHDL 4 04-06-2004 02:55 PM
Altium DXP VHDL for designing Xilinx FPGA Dieter Keldenich VHDL 0 10-18-2003 07:05 PM
XILINX FPGA project Davo VHDL 0 08-13-2003 03:32 PM
Xilinx FPGA protoboard < $200 Mark Riegert VHDL 1 07-30-2003 04:01 PM



Advertisments