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"Andrey Tarasov" <> writes:
> Hallo, Andre!
> You wrote on 07 Dec 2003 16:17:43 +0100:
>
> >> How does BridgeID than look like? If DEC has one byte for
> >> priority and IEEE - 2 bytes... 7 vs. 8 - we are one byte short.
>
> AB> I'll have a sniff as soon as I'm on location or reactivate
> AB> such device in the lab or a class.
>
> I'll really appreciate if you will post your findings.

I expect I'm going to be able to sniff that to the bottom in an L1/L2
class next month.

> AB> BTW, those ancient or at least old boxes may have had their
> AB> specialties, but at least they never broke in a way that I've
> AB> now seen with several different Cisco gear from 35xxXL through
> AB> 3550 to 6509: The CPU dies and thus STP ceases, but the lower
> AB> switch functions stay alive. The result should be obvious...
>
> Do you mean that CPU physically dies or just hit 100% utilization?

In cases of the 3500XL and 3550, it appeared to be a physical knockout
of the CPU after sum runtime. The box ist alive and kicking, but all of
a sudden, it doesn't answer anything CPU-related (dead console, dead IP,
dead STP). The ports and switching paths stay in exactly the same way
they where before the CPU died. In case of the 6509, I had an incorrect
confreg on the Supervisor (had "BREAK has effect" set), while the confreg
on the MSFC2 was well. When the console port received a BREAK, the Sup
went down to rommon, with the MSFC2 starting to cry about the watchdog
not seeing the Sup anymore and finally following the Sup 120s later.
At that time, the switch matrix seemed to continue to switch on the
paths established before the brains gone to rommon consciouslessness...

> I recently had very unpleasant experience with WS-X6408 which didn't
> died completely but merely ceased to receive any frames. Considering
> the fact that we've had 6 floor switches connected to this blade I
> learned value of having UDLD configured on
> inter-switch ports in a hard way

Sounds like a similar problem. It appears any modern switch architecture
(consisting of a controlling CPU and an ASIC-based switch matrix) is to
some extend sensitive to the CPU dropping out of service. I'd expect the
designers to integrate some sort of "reverse watchdog" into the ASICs,
one that lets them cease any operation if not constantly beaten upon the
head by the CPU. It should be hardwired into the most basic operation
protocols between the CPU and the ASICs IMO...

--
The _S_anta _C_laus _O_peration
or "how to turn a complete illusion into a neverending money source"

-> Andre "ABPSoft" Beck +++ ABP-RIPE +++ Dresden, Germany, Spacetime <-