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Modelsim SE Simulation Question

 
 
Simon Heinzle
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      07-19-2006
Hi comp.lang.vhdl Reader!

Following problem: after simulating for quite a while, I often realize that
I forgot to add some important signals to the wave window.

Normal procedure then is e.g. "restart; run 1 ms", which takes quite some
time, altough neither the input vectors nor the circuit is altered.

I just found out that there exist checkpoints ("checkpoint filename" to
create a checkpoint, "restore filename" to go back to that saved state), but
that cannot be the final solution.

Is there a better way to speed up/recover the missing signals in such a
situation?

Thanks,
Simon


 
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Martin Thompson
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      07-19-2006
"Simon Heinzle" <(E-Mail Removed)> writes:

> Hi comp.lang.vhdl Reader!
>
> Following problem: after simulating for quite a while, I often realize that
> I forgot to add some important signals to the wave window.
>


I do a "log -r /*" before running the sim then all the data is logged,
ready for me to add it to the wave window.

Obviously if you are doing enormous designs, this may well eat your
harddisk, but it works fine on our video-processing designs, even on
whole-frame simulations.

Cheers,
Martin

--
http://www.velocityreviews.com/forums/(E-Mail Removed)
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt

 
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ALuPin@web.de
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      07-20-2006

> I do a "log -r /*" before running the sim then all the data is logged,
> ready for me to add it to the wave window.
>
> Obviously if you are doing enormous designs, this may well eat your
> harddisk, but it works fine on our video-processing designs, even on
> whole-frame simulations.
>


Hi Martin,

what kind of whole-frame simulation are you talking about, DVI ?

How do you stimulate your design ? With text files, bin files
which include "real" image data or just "free" data ?

I am asking because I am also trying to perform whole-frame simulations
for a DVI application.

Rgds
André

 
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Simon Heinzle
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      07-20-2006
Thanks!

Cheers,
Simon


"Martin Thompson" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> "Simon Heinzle" <(E-Mail Removed)> writes:
>
>> Hi comp.lang.vhdl Reader!
>>
>> Following problem: after simulating for quite a while, I often realize
>> that
>> I forgot to add some important signals to the wave window.
>>

>
> I do a "log -r /*" before running the sim then all the data is logged,
> ready for me to add it to the wave window.
>
> Obviously if you are doing enormous designs, this may well eat your
> harddisk, but it works fine on our video-processing designs, even on
> whole-frame simulations.
>
> Cheers,
> Martin
>
> --
> (E-Mail Removed)
> TRW Conekt - Consultancy in Engineering, Knowledge and Technology
> http://www.trw.com/conekt
>



 
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Martin Thompson
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      07-21-2006
"(E-Mail Removed)" <(E-Mail Removed)> writes:

> > I do a "log -r /*" before running the sim then all the data is logged,
> > ready for me to add it to the wave window.
> >
> > Obviously if you are doing enormous designs, this may well eat your
> > harddisk, but it works fine on our video-processing designs, even on
> > whole-frame simulations.
> >

>
> Hi Martin,
>
> what kind of whole-frame simulation are you talking about, DVI ?
>


No, it's for an automotive image-processing application. We generally
work with VGA sensors. See this for more details:
http://www.conekt.net/docs/LDW%20V1.0.pdf

> How do you stimulate your design ? With text files, bin files
> which include "real" image data or just "free" data ?
>


I take PGM (text format, easy to read) files, for which I have a VHDL
reader, and then feed them into the simulation via a model of the
camera. The PGM files either come from our real-world logged video
stream, along with the "right-answers" from the SW-based development
code, or from synthetic images, then I make up the right-answers
myself

> I am asking because I am also trying to perform whole-frame simulations
> for a DVI application.
>


What resolution?

Cheers,
Martin

--
(E-Mail Removed)
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt

 
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Bill Mills
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      07-25-2006
For collecting sim data for post-processing or viewing, try a .do
script that captures the signals of interest only on a clock or strobe
that you define:

# Run this .do file before you vsim & run.

# keep going on an error
onerror {resume}

# !!! The first signal added is STROBE 0 !!!!
add list -width 7 -label dds_clk /modulator_inst/dds_clk

# See all the "-notrigger" below?
# W/o this switch, any transition of any of the signals
# causes the list to be updated.
# But this script only updates the list when dds_clk changes!
add list -notrigger -dec -width 10 -label accu_gmsk_out
/modulator_inst/accu_gmsk_out
add list -notrigger -unsigned -label mod_out /modulator_inst/mod_out
add list -notrigger -dec -label sine /modulator_inst/nco_sin_tp
add list -notrigger -dec -label cosine /modulator_inst/nco_cos_tp
add list -notrigger -label startpwcen /modulator_inst/startpwcen
add list -notrigger -label stoppwcen /modulator_inst/stoppwcen
add list -notrigger -unsigned -label i_addr /modulator_inst/i_addr
add list -notrigger -unsigned -label q_addr /modulator_inst/q_addr
add list -notrigger -dec -label delta_i /modulator_inst/i_out
add list -notrigger -dec -label delta_q /modulator_inst/q_out

# Configure the first signal as the strobe.
configure list -usestrobe 0
configure list -strobestart {0 ps} -strobeperiod {0 ps}
configure list -delta none

Have fun!
Bill

 
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