RAM simulation models

hi,
im currently working on a project which uses a static RAM from 'issi'.
Before implementing the system in FPGA i need to simulate the whole
system including harware parts. For this im looking for a simulation
model for the SRAM 'IS61LV25616AL', which is not available from vendor
website. hence im little confused with what im doing and got following
problems.

if the system includes external harware components(RAM, sensors, etc),
how could the whole system be simulated. Is it common to use sumulatiom
models for those components in such situations. If yes, in the event of
simulation model of the component is not available, what are the
alternatives? If no how could the whole system be simulated before
synthersis?

thanks
CMOS

manusha@millenniumit.com

wrote:

> if the system includes external harware components(RAM, sensors, etc),
> how could the whole system be simulated. Is it common to use sumulatiom
> models for those components in such situations.

yes

> If yes, in the event of
> simulation model of the component is not available, what are the
> alternatives?

Write your own functional model.
Keep it simple.
http://groups.google.com/groups/sear...del+vhdl+array

-- Mike Treseler

Mike Treseler wrote:
> wrote:
>
>> if the system includes external harware components(RAM, sensors, etc),
>> how could the whole system be simulated. Is it common to use sumulatiom
>> models for those components in such situations.
>
> yes
>
>> If yes, in the event of
>> simulation model of the component is not available, what are the
>> alternatives?
>
> Write your own functional model.
> Keep it simple.
> http://groups.google.com/groups/sear...del+vhdl+array
>
> -- Mike Treseler

You can also look for a similar part at: http://www.FreeModelFoundry.com

-Rick Munden

Concerning most ISSIs, there are similar RAMs out. Furthermore: I am
sure you know, that there are some free generic RAM models around in
the inet. Some of the are parametrizeable according to the written spec
of your particular ram. This is the most effective way to obtain a
stable simulation.

For a valueable simulation, I usually use switchable models (a typical
one, and some extreme case, where data is given out too early or too
late). Thus you can make your design work also for cases outside the
RAM spec, or obtain higher security.