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[noob] signed binary

 
 
Massi
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      07-14-2006
Hi all,
little question for you:
i've this code
BINOUT <= "1111111111111111" when BININ >= "1111111111110000" and BININ <=
"0000000000001000" else

(it's an example)
how can i tell VHDL to consider that "1111...." a negative number and not a
positive one?
I tried with signed("11111....") but i get an error..
I'd like to avoid local vars because the lookup table is very big..

Thanks..
libraries loaded are

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;

and the error is

Type conversion (to signed) can not have string literal operand.

bye


 
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Jonathan Bromley
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      07-14-2006
On Fri, 14 Jul 2006 23:48:05 +0200, Massi
<(E-Mail Removed)> wrote:

> BINOUT <= "1111111111111111" when BININ >= "1111111111110000" and BININ <=
>"0000000000001000" else
>
>how can i tell VHDL to consider that "1111...." a negative number and not a
>positive one?
>I tried with signed("11111....") but i get an error..
>I'd like to avoid local vars because the lookup table is very big..
>
>Thanks..
>libraries loaded are
>
>library IEEE;
>use IEEE.std_logic_1164.all;
>use ieee.std_logic_signed.all;
>use ieee.std_logic_arith.all;


aaargh... that way lies confusion and madness.

Please get into the habit of doing The Right Thing (TM):

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- NEVER use std_logic_(un)signed
-- Avoid std_logic_arith, use numeric_std instead

Now you can have SIGNED and UNSIGNED co-existing in the same module
without difficulty or confusion; you get conversion functions with
sensible names; and you get a reasonably complete set of arithmetic
operations on SIGNED and UNSIGNED.

signed("11111111") is an error because the data type of the constant
"11111111" is not well defined. It might be a string, a bit-vector, a
std_logic_vector, an UNSIGNED, a SIGNED... and although some of
those may legally be type-converted to SIGNED, some can't.
However, "11111111" is a perfectly valid constant of type SIGNED,
so just tell the compiler what data type you want it to be:

signed'("11111111")

(note the apostrophe between signed and the opening parenthesis).

Note, also, that numeric_std allows you to compare signed or unsigned
things directly with integers; so you could much more elegantly
write your example (assuming BININ is of type SIGNED):

BINOUT <= "1111111111111111"
when (BININ >= -16) and (BININ <=
else...

If BININ is a port of std_logic_vector type (a common situation) then
you will need to type-convert it to SIGNED for this to work:

signal S_BININ: SIGNED(BININ'range);
....
S_BININ <= SIGNED(BININ);

and now you do all your SIGNED tests on S_BININ.

Finally, instead of the true ghastliness of
BINOUT <= "1111111111111111";
please consider writing a handy conversion function:

subtype t_binout is signed(BINOUT'range);
function to_binout(n: integer) return t_binout is begin
return to_signed(n, t_binout'length);
end;

and then you can easily write
BINOUT <= to_binout(-1);

If you find that all this type conversion and functions stuff is just
too much, you can instead respond to the siren calls of Verilog.
It'll be SOOOO much easier for the first few months. Only after
the first few years will you start to notice that maybe VHDL's
type system isn't such a bad thing after all...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
http://www.velocityreviews.com/forums/(E-Mail Removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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Mike Treseler
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      07-14-2006
Massi wrote:

> libraries loaded are
> library IEEE;
> use IEEE.std_logic_1164.all;
> -- use ieee.std_logic_signed.all;
> -- use ieee.std_logic_arith.all;

use ieee.numeric_std.all;


http://groups.google.com/groups/sear...ic_std+example


-- Mike Treseler
 
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Massi
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      07-14-2006
Jonathan Bromley wrote:
> [cut]


lol
thank you very VERY much for your help

I must admin i did not understand much of your post but I did this

> signal S_BININ: SIGNED(BININ'range);
> ...
> S_BININ <= SIGNED(BININ);


and THAN this

> signed'("11111111")


and all seems to work fine..

BUT you are not safe yet

I did a little testbench, and even if every "right" value works fine, a
"wrong" value give me this error

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
result will be 'X'(es).
# Time: 274222530 ns Iteration: 0 Instance: /tb_testdiscretizer
# Test FAILED:

something to do with my last "else" tense?

(others => '-');

And the last thing

> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
> -- NEVER use std_logic_(un)signed
> -- Avoid std_logic_arith, use numeric_std instead


so all i need is
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
?

Thank you SO much


 
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Ralf Hildebrandt
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      07-15-2006
Massi wrote:

> # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
> result will be 'X'(es).
> # Time: 274222530 ns Iteration: 0 Instance: /tb_testdiscretizer
> # Test FAILED:
>
> something to do with my last "else" tense?
>
> (others => '-');


Yes. Integers do not have these Values. Therefore something is lost
during conversion and this warning tells you this.

The workaround is to avoid the conversion of a std_(u)logicvector /
signed / unsigned to integer. Often this can be done converting the
integer in the opposite direction.

Example:

signal my_vec : std_ulogic_vector(bitwidth-1 downto 0);

if (to_integer(signed(my_vec)) = 42) then

if (my_vec = std_ulogic_vector(to_signed(42,my_vec'length))) then

The 2nd if-clause will not give such warnings.



Ralf
 
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Massi
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      07-15-2006
Ralf Hildebrandt wrote:

> Yes. Integers do not have these Values. Therefore something is lost
> during conversion and this warning tells you this.


uhm.. i don't think there is any conversion to integer..
at least, i didn't want to do that lol
So, i've a std_logic_vector as output, and the value assigned depends on
many "where" conditions
When no "where" is true, i want to assign the value "-------" (and
std_logic_vector DOES have this value, right?)
So, what's the correct way to do that?
Or maybe have i not to assign a value to the output when no condition is
true? i don't think that's a great solution..

thank you


 
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Jonathan Bromley
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      07-15-2006
On Sat, 15 Jul 2006 00:52:40 +0200, Massi
<(E-Mail Removed)> wrote:

>I must admin i did not understand much of your post


Sorry, that wasn't intentional

> but I did this
>
>> signal S_BININ: SIGNED(BININ'range);
>> ...
>> S_BININ <= SIGNED(BININ);

>
>and THAN this
>
>> signed'("11111111")

>
>and all seems to work fine..


yes, it's a good thing to do

>BUT you are not safe yet
>
>I did a little testbench, and even if every "right" value works fine, a
>"wrong" value give me this error
>
># ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
>result will be 'X'(es).
># Time: 274222530 ns Iteration: 0 Instance: /tb_testdiscretizer
># Test FAILED:
>
>something to do with my last "else" tense?
>
>(others => '-');


"-----" is OK as a value for a SIGNED or UNSIGNED vector.
Are you trying to do some other arithmetic operation with
this value? If you are, then it's probably correct for the result
to be X, because you don't know (don't care) what the value is,
so you don't know (don't care) what the result is.

>And the last thing
>
>so all i need is
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
>?


Absolutely correct.

std_logic_(un)signed are convenient for some very
simple situations (like writing a counter using a std_logic_vector)
but they are very limited and restrictive, so I always recommend
that you should not use them. (Some people disagree.)

std_logic_arith is an older version of numeric_std.
numeric_std is better in every way, so there is no sense in using
std_logic_arith unless it's needed to maintain an old design.

Would the nice people at Xilinx (and possibly others), who set
their VHDL editors to have std_logic_unsigned+std_logic_arith
as the default, please make themselves known so that we can
shout at them very loudly? Thanks!
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(E-Mail Removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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Massi
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      07-15-2006
Jonathan Bromley wrote:

>> I must admin i did not understand much of your post

> Sorry, that wasn't intentional


That's because i'm so noob

> "-----" is OK as a value for a SIGNED or UNSIGNED vector.
> Are you trying to do some other arithmetic operation with
> this value? If you are, then it's probably correct for the result
> to be X, because you don't know (don't care) what the value is,
> so you don't know (don't care) what the result is.


mmm. no..
no arithmetic operation, i just have to set a std_logic_vector value to
"-------", just to understand that this value is "wrong"..
And it seems i cannot get this to work..

Example:

BINOUT <= "1111" when BININ >= "0001" and BININ <= "1100"
else (others => '-');

and this gives an error..

> std_logic_(un)signed are convenient for some very
> simple situations (like writing a counter using a std_logic_vector)
> but they are very limited and restrictive, so I always recommend
> that you should not use them. (Some people disagree.)
> std_logic_arith is an older version of numeric_std.
> numeric_std is better in every way, so there is no sense in using
> std_logic_arith unless it's needed to maintain an old design.


I will follow my master's way and i will always use only those libraries


 
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Ralf Hildebrandt
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      07-15-2006
Massi wrote:


>> Yes. Integers do not have these Values. Therefore something is lost
>> during conversion and this warning tells you this.


> uhm.. i don't think there is any conversion to integer..
> at least, i didn't want to do that lol
> So, i've a std_logic_vector as output, and the value assigned depends on
> many "where" conditions
> When no "where" is true, i want to assign the value "-------" (and
> std_logic_vector DOES have this value, right?)
> So, what's the correct way to do that?


Yes, that is a correct way.
But if you seek for logic reduction it is better to assign (others=>'X')
to the vector.


Neverteheless aus you have written in your 1st post

> BINOUT <= "1111111111111111" when BININ >= "1111111111110000" and BININ <=
> "0000000000001000" else


there _are_ some arithmetic operations (the comparisons). Arithemetic
operations can be easily performed if you use signed, unsigned or
integer as type.
And to make the next step: arithmetic operations should be never done
with std_(u)logic_vectors, because it is ambiguous whether the operand
is treated as to be a signed or unsigned vector. Manual conversions to
the type signed or unsigned clear the ambiguity.

Ralf
 
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Massi
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      07-16-2006
Jonathan Bromley wrote:
> [cut]


i go on having BIG troubles with this malicious vhdl

I've to create some simple code (the big part of the project is in C++) but
i always have much problems with signed values...

The first part of the project is this (almost functional, but the "others
=>" isn't working)

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity name is
port(
BININ : in std_logic_vector(0 to 3);
BINOUT : out std_logic_vector(0 to 3)
);
end name;
architecture rrgen of name is
signal S_BININ: SIGNED(BININ'range);
begin
S_BININ <= SIGNED(BININ);
BINOUT <= "1111" when S_BININ >= signed'("1001") and S_BININ <=
signed'("0100") else
(others => '-');
end rrgen;

As i said before, this block is working, excepting the "default" value
"others=>'-'"
Is there any error in this code? may i change anything?

And then, the HARD block

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity unnamed is
port(
BININ : in std_logic_vector(0 to 3);
BINOUT : out std_logic_vector(0 to 3)
);
end unnamed;

architecture rrgen of unnamed is
constant pi : std_logic_vector(0 to 3) := "1010";
constant duepi : std_logic_vector(0 to 3) := "1010";
constant pimezzi : std_logic_vector(0 to 3) := "0101";
signal S_PI: SIGNED(pi'range);
signal S_DUEPI: SIGNED(duepi'range);
signal S_PIMEZZI: SIGNED(pimezzi'range);
signal S_BININ: SIGNED(BININ'range);

begin
S_PI <= SIGNED(pi);
S_DUEPI <= SIGNED(duepi);
S_PIMEZZI <= SIGNED(pimezzi);
S_BININ <= SIGNED(BININ);

while S_BININ < -S_PI loop
S_BININ <= S_BININ + S_DUEPI;
end loop;
while S_BININ > S_PI loop
S_BININ <= S_BININ - S_DUEPI;
end loop;

BINOUT <= S_PI-S_BININ when S_BININ > S_PIMEZZI else
-S_PI-S_BININ when S_BININ < -S_PIMEZZI else
S_BININ;
end rrgen;

and, simply, nothing works...
i get errors in the while, in the assignment, in the operators, everywhere!

What drives me crazy is that the "target" of this module is SO SIMPLE, but
so hard (for me..) to obtain.. i befin hating signed numbers

thanks very very much to everyone will try to help me..
I hope Jonathan will loose some time with me.. again


 
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