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VHDL - Generic: use constant or not?

 
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Old 07-14-2006, 05:41 PM   #1
Default Generic: use constant or not?


Hello,

The generic part of entity declaration. I've found that there are two
ways, like:

GENERIC ( constant value : integer := 5 )

or

GENERIC ( value : integer := 5 )

Both ways seem to work fine, for synthesis and simulation. I suppose
they are equivalent. Wich difference the "constant" do? Any comments?

Regards,

Ricardo.



Ricardo
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Old 07-14-2006, 06:41 PM   #2
Mike Treseler
 
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Default Re: Generic: use constant or not?

Ricardo wrote:

> The generic part of entity declaration. I've found that there are two
> ways, like:
> GENERIC ( constant value : integer := 5 )
> or
> GENERIC ( value : integer := 5 )
>
> Both ways seem to work fine, for synthesis and simulation. I suppose
> they are equivalent.


yes

Wich difference the "constant" do? Any comments?


I leave out the "constant" because
a generic cannot be of any other class.
If someday there are other options
(generic types would be nice!), I expect
that constant will still be the default class.

-- Mike Treseler




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Old 07-18-2006, 12:19 PM   #3
=?ISO-8859-1?Q?Sch=FCle_Daniel?=
 
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Default Re: Generic: use constant or not?

Ricardo schrieb:
> Hello,
>
> The generic part of entity declaration. I've found that there are two
> ways, like:
>
> GENERIC ( constant value : integer := 5 )
>
> or
>
> GENERIC ( value : integer := 5 )
>
> Both ways seem to work fine, for synthesis and simulation. I suppose
> they are equivalent. Wich difference the "constant" do? Any comments?


from my book 'A VHDL primer'
"A generic declares constant object of mode -in-"

whether you write constant or not, it's constant per default
the same is true for procedures

procedure test(a: in bit, b: out bit);
if object class is omited then parameters with
-in- mode are implicitely constant and thoese with
-inout- or -out- mode are variable's and could be written as

procedure test(constant a: in bit, variable b: out bit);

if one wants b to be signal this should be then

procedure test(constant a: in bit, signal b: out bit);

hth, Daniel
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