Floating point operations in vhdl.

Hello,
I am looking for effectiv vhdl floating point type.
I need make "+" and "*" operations.
It would be fine if that type had changed (as parameter) bit precision
had 8 to 20 bits.

Thank you for any answer.

Best regards,
Mariusz

MariuszK

Hi

Try float_pkg_c.vhd from http://www.eda-stds.org/fphdl/

David Bishop is working on fixed and floating point libraries which
will be part of VHDL-2006 from IEEE. The file above is a compatibility
version of these libraries designed to work with current synthesis and
simulation tools (which naturally don't support VHDL-2006).

I use the fixed point version and it works great. The nice part is that
it will soon be part of a IEEE standard.

If you plan to synthesize, be warned that floating point operations in
general take up plenty of space.

If you have trouble getting the library to compile, let me know.
Richard

napisal(a):
> Hi
>
> Try float_pkg_c.vhd from http://www.eda-stds.org/fphdl/
>
> David Bishop is working on fixed and floating point libraries which
> will be part of VHDL-2006 from IEEE. The file above is a compatibility
> version of these libraries designed to work with current synthesis and
> simulation tools (which naturally don't support VHDL-2006).
>
> I use the fixed point version and it works great. The nice part is that
> it will soon be part of a IEEE standard.
>
> If you plan to synthesize, be warned that floating point operations in
> general take up plenty of space.
>
> If you have trouble getting the library to compile, let me know.
> Richard

Hello,
Thanks. It is looks very interesting.

But how is libraries behave in case multiplication "*"?
What is frequency?
I don't find any pipeline option (make multiplication with higher
freqency but in few clock tact).
Thank you for answer
Mariusz

"MariuszK" <> wrote in message
news: ups.com...
> Hello,
> I am looking for effectiv vhdl floating point type.
> I need make "+" and "*" operations.
> It would be fine if that type had changed (as parameter) bit precision
> had 8 to 20 bits.

If you are targeting Xilinx FPGAs, there are Floating Point operator cores
available from the core generator. They are fully parameterizable in both
precision and latency. You can instantiate them in VHDL (they won't be
automatically inserted by synthesis, I'm afraid).

If you are targeting some other FPGA or ASIC technology, then of course this
will not help you!

Cheers,

-Ben-

Ben Jones napisal(a):
> "MariuszK" <> wrote in message
> news: ups.com...
> > Hello,
> > I am looking for effectiv vhdl floating point type.
> > I need make "+" and "*" operations.
> > It would be fine if that type had changed (as parameter) bit precision
> > had 8 to 20 bits.
>
> If you are targeting Xilinx FPGAs, there are Floating Point operator cores
> available from the core generator. They are fully parameterizable in both
> precision and latency. You can instantiate them in VHDL (they won't be
> automatically inserted by synthesis, I'm afraid).
>
> If you are targeting some other FPGA or ASIC technology, then of course this
> will not help you!
>
> Cheers,
>
> -Ben-
Hello,
I want use Xilinx FPGAs.
Could you precise where can I find that core generator.
What tools do you use?

Sorry. I do not understand yours sentence.
"You can instantiate them in VHDL (they won't be automatically inserted
by synthesis, I'm afraid)."

Best Regards
Mariusz

Hi Mariusz,

"MariuszK" <> wrote in message
news: oups.com...
>
> Ben Jones napisal(a):
> > "MariuszK" <> wrote in message
> > news: ups.com...
> > > Hello,
> > > I am looking for effectiv vhdl floating point type.
> > > I need make "+" and "*" operations.
> > > It would be fine if that type had changed (as parameter) bit precision
> > > had 8 to 20 bits.
> >
> > If you are targeting Xilinx FPGAs, there are Floating Point operator
cores
> > available from the core generator. They are fully parameterizable in
both
> > precision and latency. You can instantiate them in VHDL (they won't be
> > automatically inserted by synthesis, I'm afraid).
> >
> I want use Xilinx FPGAs.
> Could you precise where can I find that core generator.
> What tools do you use?

The Core Generator is part of the ISE tool suite from Xilinx. It is also
available from the free "Webpack" edition of the tools. You can read all
about it at the Xilinx website.

> Sorry. I do not understand yours sentence.
> "You can instantiate them in VHDL (they won't be automatically inserted
> by synthesis, I'm afraid)."

So what I mean is, to use these operators you would have to instantiate them
as components and wire up the ports into your design. You cannot just write
"c <= a * b" and have the synthesis tool create a floating-point multiplier
(not yet, anyway). Instead you would write something like:

my_mult : fp_multiplier
generic map (...)
port map
( clk => clock,
a => a,
b => b,
result => c
...
);

Hope that helps.

-Ben-

[vhdlfan]

Originally Posted by Ben Jones

Hi Mariusz,

"MariuszK" <> wrote in message
news: oups.com...
>
> Ben Jones napisal(a):
> > "MariuszK" <> wrote in message
> > news: ups.com...
> > > Hello,
> > > I am looking for effectiv vhdl floating point type.
> > > I need make "+" and "*" operations.
> > > It would be fine if that type had changed (as parameter) bit precision
> > > had 8 to 20 bits.
> >
> > If you are targeting Xilinx FPGAs, there are Floating Point operator
cores
> > available from the core generator. They are fully parameterizable in
both
> > precision and latency. You can instantiate them in VHDL (they won't be
> > automatically inserted by synthesis, I'm afraid).
> >
> I want use Xilinx FPGAs.
> Could you precise where can I find that core generator.
> What tools do you use?

The Core Generator is part of the ISE tool suite from Xilinx. It is also
available from the free "Webpack" edition of the tools. You can read all
about it at the Xilinx website.

> Sorry. I do not understand yours sentence.
> "You can instantiate them in VHDL (they won't be automatically inserted
> by synthesis, I'm afraid)."

So what I mean is, to use these operators you would have to instantiate them
as components and wire up the ports into your design. You cannot just write
"c <= a * b" and have the synthesis tool create a floating-point multiplier
(not yet, anyway). Instead you would write something like:

my_mult : fp_multiplier
generic map (...)
port map
( clk => clock,
a => a,
b => b,
result => c
...
);

Hope that helps.

-Ben-

Hi,
I downloaded the fplibrary from www.ens-lyon.fr/LIP/Arenaire/Ware/FPLibrary and i was able to synthesize it. The problem i am having is that i dont know how to use it in my code. Forexample, if i want to Add two floating point number, how do i write the statement in vhdl.

is it:
tvar <= Add(A, B);

please could you advise me on what to do. What data type do i declare A, B, tvar. I am trying to download my code to xilinx board.

[vhdlfan]

I quess my question is how do i instantiate the operation when i download fp library either from www.ens-lyon.fr/LIP/Arenaire/Ware/FPLibrary or http://www.eda-stds.org/fphdl/ please help.

[shaz.cute86]

Hi everybody,

Anybody can help me..??...
I want VHDL code for floating point division...
Please help me......

Rgds,
Siti...