subprogram parameter list

Hello,

I have a simple question and my book doesn't have the answer

given a procedure declaration in the package and
its definition in a package body


package X is
procedure xxx(variable a: out integer); -- a
end;

package body X is
procedure xxx(variable b: out integer) is -- b --(2)
begin
b := 1; -- (1)
end;
end;

is it allowed to rename the parameters in such way?
ghdl gives an error message at (1) that 'b' is not declared
however (2) was accepted.

Regards, Daniel

=?ISO-8859-1?Q?Sch=FCle_Daniel?=

Schüle Daniel wrote:
> Hello,
>
> I have a simple question and my book doesn't have the answer
>
> given a procedure declaration in the package and
> its definition in a package body
>
>
> package X is
> procedure xxx(variable a: out integer); -- a
> end;
>
> package body X is
> procedure xxx(variable b: out integer) is -- b --(2)
> begin
> b := 1; -- (1)
> end;
> end;
>
> is it allowed to rename the parameters in such way?
> ghdl gives an error message at (1) that 'b' is not declared
> however (2) was accepted.
>
> Regards, Daniel

No, it is not allowed, the procedure declaration is the interface to
the procedure implementation in the package body. How will ghdl know
the procedure body matches the interface declaration. By the way,
procedures in VHDL can be overloaded. To extend your example:

package X is
procedure xxx(variable a: out integer); -- a
procedure xxx(variable a: out real); -- a
end;

package body X is
procedure xxx(variable a: out integer) is -- b --(2)
begin
b := 1; -- (1)
end;
procedure xxx(variable a: out real) is -- b --(2)
begin
b := 1.0; -- (1)
end;
end;

reuven schrieb:
> Schüle Daniel wrote:
>> Hello,
>>
>> I have a simple question and my book doesn't have the answer
>>
>> given a procedure declaration in the package and
>> its definition in a package body
>>
>>
>> package X is
>> procedure xxx(variable a: out integer); -- a
>> end;
>>
>> package body X is
>> procedure xxx(variable b: out integer) is -- b --(2)
>> begin
>> b := 1; -- (1)
>> end;
>> end;
>>
>> is it allowed to rename the parameters in such way?
>> ghdl gives an error message at (1) that 'b' is not declared
>> however (2) was accepted.
>>
>> Regards, Daniel
>
> No, it is not allowed, the procedure declaration is the interface to
> the procedure implementation in the package body. How will ghdl know
> the procedure body matches the interface declaration.


I think it is more a matter of design
it would be easy to ignore the name the way C does it

int foo(int x);
int foo(int y);
int foo(int); // all the same

hence my question, whether the names are part of subprogram
signature or not.

I stumbled over this with names res <-> ret (meaning result <-> return)


By the way,
> procedures in VHDL can be overloaded. To extend your example:
>
> package X is
> procedure xxx(variable a: out integer); -- a
> procedure xxx(variable a: out real); -- a
> end;

yes, I use it heavily

BTW is it possible to overload a function on its return type?
(something that can't be done in C++)

Regards, Daniel

Schüle Daniel a écrit :

> reuven schrieb:
> > Schüle Daniel wrote:
> >> Hello,
> >>
> >> I have a simple question and my book doesn't have the answer
> >>
> >> given a procedure declaration in the package and
> >> its definition in a package body
> >>
> >>
> >> package X is
> >> procedure xxx(variable a: out integer); -- a
> >> end;
> >>
> >> package body X is
> >> procedure xxx(variable b: out integer) is -- b --(2)
> >> begin
> >> b := 1; -- (1)
> >> end;
> >> end;
> >>
> >> is it allowed to rename the parameters in such way?
> >> ghdl gives an error message at (1) that 'b' is not declared
> >> however (2) was accepted.
> >>
> >> Regards, Daniel
> >
> > No, it is not allowed, the procedure declaration is the interface to
> > the procedure implementation in the package body. How will ghdl know
> > the procedure body matches the interface declaration.
>
>
> I think it is more a matter of design
> it would be easy to ignore the name the way C does it
>
> int foo(int x);
> int foo(int y);
> int foo(int); // all the same
>
> hence my question, whether the names are part of subprogram
> signature or not.
Yes they are! Cf LRM 2.7

> I stumbled over this with names res <-> ret (meaning result <-> return)
>
>
> By the way,
> > procedures in VHDL can be overloaded. To extend your example:
> >
> > package X is
> > procedure xxx(variable a: out integer); -- a
> > procedure xxx(variable a: out real); -- a
> > end;
>
> yes, I use it heavily
>
> BTW is it possible to overload a function on its return type?
> (something that can't be done in C++)
Yes it is. LRM 10.5

JD.