VHDL Newbie - Is this a valid statement?

Hello,

My goal is to make a step in my FSM that loops until my counter reaches
it's desired value and then moves to it's next step - however I am
having issues detecting it reaching that desired value. I'm assuming
that something is wrong with my conditional statement. Can you compare
a signal against a constant value in VHDL

signal counter_q: std_logic_vector(3 downto 0);
......
when read_del =>

cnt_rst <='0'; -- signal to reset counter - keep low here

if(counter_q(3 downto 0) = "1101") THEN
next_state <= blah;
else
next_state <= read_del;
end if;

What is the proper way to preform this action?

Thanks in advance

nigel502@gmail.com

wrote:

> Can you compare
> a signal against a constant value in VHDL

You can compare a signal's *previous value*.
I find using the *present value* of a process variable
easier to understand.

> What is the proper way to preform this action?

That's debatable.
For the way I do it,
see the procedure tx_state in the reference design here:
http://home.comcast.net/~mike_treseler/

-- Mike Treseler

> I find using the *present value* of a process variable
> easier to understand.

could you provide an example of this?

wrote:
>>I find using the *present value* of a process variable
>>easier to understand.
>
>
> could you provide an example of this?
>
see the procedure tx_state in the reference design here:
http://home.comcast.net/~mike_treseler/

I have looked at this example - but in that procedure I can only see
comparision of 1 bit of a signal as compared to 4 bits.

I don't see any problems with the state machine you wrote, everything
seems fine. Unless you mentioned something else.
You stay in the read_del state untill the counter has the value "1101".
If the counter reached that value, your next state is blah and the
counter probably has the value "1110".

If not, you best give me the rest of your FSM.

wrote:

> What is the proper way to preform this action?

You haven't provided enough information.

"...having issues detecting it..." - what exactly do you mean? Compile
errors? Or just doesn't appear to work? Does counter_q increment?

You haven't explained how you are clocking counter_q, or the state
machine itself! How/where are you incrementing counter_q?

As an aside, I prefer to assign default values to signals to reduce the
number of 'else' statements required - which can be quite significant in
large state machines!

ie.
next_state <= state;
case (state) is
when read_del =>
if counter_q(3 downto 0) = "1101" then
next_state <= blah;
end if;

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Hi Nigel,
your source snippet seems to be ok. If your design isn't time critical
you can leave it the way it is.

To use a reset inside a design as a control signal is a philosophical
question.
But doing the compare inside your fsm increases the number of inputs
unnecessary. Better do that inside your counter and generate a
(synchronous) CountEnd signal there. This may speed up your FSM a little.


Comparing signals to constants is very common in VHDL. If your counter
has only four bits anyway it's sufficient to write
if(counter_q = "1101") THEN
...
end if;

One thing that may bother you is the chosen value. Is cnt_rst a
synchronous or an asynchronous input to the counter? If it's a
synchronous reset your counter may stay one count behind the expected
value (pipelinig effect, check your simulation). To overcome this you
can simply reduce the compare constant.

have a nice synthesis
Eilert




schrieb:
> Hello,
>
> My goal is to make a step in my FSM that loops until my counter reaches
> it's desired value and then moves to it's next step - however I am
> having issues detecting it reaching that desired value. I'm assuming
> that something is wrong with my conditional statement. Can you compare
> a signal against a constant value in VHDL
>
> signal counter_q: std_logic_vector(3 downto 0);
> .....
> when read_del =>
>
> cnt_rst <='0'; -- signal to reset counter - keep low here
>
> if(counter_q(3 downto 0) = "1101") THEN
> next_state <= blah;
> else
> next_state <= read_del;
> end if;
>
> What is the proper way to preform this action?
>
> Thanks in advance
>

> have a nice synthesis

All,

Thank you very much for your help - I didn't realize it until I read
this last line that I hadn't included these signals in my synthesis,
and that was why my FSM was constantly looping when I synthesis.

Once again, thank you all for you quick responses,

nigel

backhus wrote:
> Hi Nigel,
> your source snippet seems to be ok. If your design isn't time critical
> you can leave it the way it is.
>
> To use a reset inside a design as a control signal is a philosophical
> question.
> But doing the compare inside your fsm increases the number of inputs
> unnecessary. Better do that inside your counter and generate a
> (synchronous) CountEnd signal there. This may speed up your FSM a little.
>
>
> Comparing signals to constants is very common in VHDL. If your counter
> has only four bits anyway it's sufficient to write
> if(counter_q = "1101") THEN
> ...
> end if;
>
> One thing that may bother you is the chosen value. Is cnt_rst a
> synchronous or an asynchronous input to the counter? If it's a
> synchronous reset your counter may stay one count behind the expected
> value (pipelinig effect, check your simulation). To overcome this you
> can simply reduce the compare constant.
>
> have a nice synthesis
> Eilert
>
>
>
>
> schrieb:
> > Hello,
> >
> > My goal is to make a step in my FSM that loops until my counter reaches
> > it's desired value and then moves to it's next step - however I am
> > having issues detecting it reaching that desired value. I'm assuming
> > that something is wrong with my conditional statement. Can you compare
> > a signal against a constant value in VHDL
> >
> > signal counter_q: std_logic_vector(3 downto 0);
> > .....
> > when read_del =>
> >
> > cnt_rst <='0'; -- signal to reset counter - keep low here
> >
> > if(counter_q(3 downto 0) = "1101") THEN
> > next_state <= blah;
> > else
> > next_state <= read_del;
> > end if;
> >
> > What is the proper way to preform this action?
> >
> > Thanks in advance
> >