Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Problem while doing PAR simulation.

Reply
Thread Tools

Problem while doing PAR simulation.

 
 
Srikanth
Guest
Posts: n/a
 
      06-27-2006
Hi all,
I am using Xilinx 7.1 ISE . I am facing a problem while doing post
place and route simulation.
I am using model sim 6.0 version. I get the following error while doing
post place simulation
"An error occurred while executing
D:/programfiles/xilinx/data/projnav/scripts/TclFileWrapper4Halite.tcl."
Has anybody faced a similar problem or has an idea about why is it
coming?
Thanks in advance,
Srikanth

 
Reply With Quote
 
 
 
 
Mike Treseler
Guest
Posts: n/a
 
      06-28-2006
Srikanth wrote:

> I am using Xilinx 7.1 ISE . I am facing a problem while doing post
> place and route simulation.
> I am using model sim 6.0 version. I get the following error while doing
> post place simulation
> "An error occurred while executing
> D:/programfiles/xilinx/data/projnav/scripts/TclFileWrapper4Halite.tcl."
> Has anybody faced a similar problem


For a synchronous design that passes
static timing and functional simulation,
there is no good reason to run a gate simulation.

If you want to run one anyway,
work from the modelsim prompt
or write your own tcl scripts.

-- Mike Treseler

 
Reply With Quote
 
 
 
 
mk
Guest
Posts: n/a
 
      06-28-2006
On Wed, 28 Jun 2006 07:10:11 -0700, Mike Treseler
<(E-Mail Removed)> wrote:

>Srikanth wrote:
>
>> I am using Xilinx 7.1 ISE . I am facing a problem while doing post
>> place and route simulation.
>> I am using model sim 6.0 version. I get the following error while doing
>> post place simulation
>> "An error occurred while executing
>> D:/programfiles/xilinx/data/projnav/scripts/TclFileWrapper4Halite.tcl."
>> Has anybody faced a similar problem

>
>For a synchronous design that passes
>static timing and functional simulation,
>there is no good reason to run a gate simulation.


Because you said gate simulation I am assuming that you mean RTL level
for functional simulation; if so that's not entirely safe. You need to
add formal verification between rtl & gate to make sure you're
covered. Another way is to run gate level simulations without timing
(nospecify + zero delay) to at least check for the gate level
correctness for the paths you're taking in your tests (which should
have pretty good coverage anyway).
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Can't find par loader at C:/Perl/site/lib/PAR/Packer.pm line 101 Oliver Soeder Perl Misc 1 06-30-2007 02:32 PM
Can't find par loader at C:/Perl/site/lib/PAR/Packer.pm line 101. osoeder@gmx.de Perl Misc 0 06-07-2007 02:58 PM
PAR, PAR::Packer smueller@cpan.org Perl Misc 1 12-01-2006 09:41 PM
Data type conversion problem between java and C while doing JNI... JPractitioner Java 5 08-08-2006 07:01 AM
message eradique par une regle emise par SPE interscaneManager@fr.ch Python 0 08-21-2003 07:47 PM



Advertisments