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Hi,

I'm trying to access a single element of a std_logic_vector, and I am
getting this error from ISE (6.3i):

"FATAL_ERROR:Xst:listutil.c:503:1.19 - Data corruption (ListDelShift) -
Bad Index Process will terminate. To resolve this error, please
consult the Answers Database and other online resources at
http://support.xilinx.com. If you need further assistance, please open
a Webcase by clicking on the "WebCase" link at
http://support.xilinx.com"

The code that generates this is:

process(output_enable)
variable temp_weight :
std_logic_vector(weight_precision - 1 downto 0);
begin
if config_enable='0' then
for i in weight_precision - 1 downto 0 loop
temp_weight(i) := weight_table(0); <== ERROR HERE
end loop;

weight <= SXT(temp_weight, adder_input_width);
end if;
end process;

The error would appear to refer to the "weight_table(0)" statement.
Normally, I don't reference just the 0'th element - I use an expression
to calculate the bit I need - but the error still occurs. The error
occurs with other indices (such as 1,2,3 etc, and also
"weight_table'length - 1") too.

weight_table is defined as:
"signal weight_table : std_logic_vector(weight_table_left downto 0)"
where "weight_table_left" is 63 in this case.

"weight_table" is initialised to all zeros.

I'm sure it is something simple, but I just can't see it. Can anyone
help?

Many thanks,
Robin

What does simulation say? It is usually a lot easier to determine the
cause of bad indexing in simulation.

There are several signals missing from your sensitivity list, but I
doubt that would cause your problem in synthesis.

For safety's sake, I usually try to use an array's 'range attribute as
the loop index specification. That way I know that the index will not
be out of bounds on the array.

Andy

Hi Andy,

I'm not sure that I can simulate the code as the error occurs during
synthesis...

As for the range, the value is question is the "weight_table" signal -
which in the code I posted has a fixed index. I know it must be this
that is causng the error as I have removed the other parts of the code
through a process of elimination.

Does that help to shed any light on the problem?

Thanks,
Robin

Andy wrote:
> What does simulation say? It is usually a lot easier to determine the
> cause of bad indexing in simulation.
>
> There are several signals missing from your sensitivity list, but I
> doubt that would cause your problem in synthesis.
>
> For safety's sake, I usually try to use an array's 'range attribute as
> the loop index specification. That way I know that the index will not
> be out of bounds on the array.
>
> Andy

Robin Emery wrote:

> I'm not sure that I can simulate the code as the error occurs during
> synthesis...

I'm sure you can, if you have a vhdl simulator.

-- Mike Treseler

hi
i think Mike is right. it is not always that, if your code is not
getting synthesis means it wont get simulate. i think you should try
to simulate. if there wont be an error, at least you will get warnings
from simulator. so please try to simulate first.


Mike Treseler wrote:
> Robin Emery wrote:
>
> > I'm not sure that I can simulate the code as the error occurs during
> > synthesis...
>
> I'm sure you can, if you have a vhdl simulator.
>
> -- Mike Treseler

You have a number of problems in the code that you posted....

1. What is 'weight_precision'? By it's usage it would appear to most
likely be a constant, but who knows?
2. The process lists the signal 'output_enable' in the sensitivity list
but that signal is not used in the process so it shouldn't be there.
3. config_enable IS used in the process but is not in the sensitivity
list.
4. weight_table IS used in the process but is not in the sensitivity
list.
5. adder_input_width IS used in the process but is not in the
sensitivity list.

Clean up those problems and as has been suggested run it on a
simulator.

KJ