latch warning...

hi, all,

when I compile a desing, I met the following warning(part of all):
"Warning: Latch next_state.st_server has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal
pre_state.st_server
Warning: Latch b_s has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal
pre_state.st_6
Warning: Latch a_s has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal
pre_state.st_2"

I try to use clock to avoid the latch problem, and it works.
but I can't understand the meaning of the warnings.

what means that : ports D and ENA are fed by the same signal?
pre_state.st_server is just a state, a condition to enter the
corresponding state. and also, I can't understand which one is fed by
the same signal.

can anyone explain what a latch really works, and how many latchs are
there in the following code section? Thank you!!!

Regards!
-- Noah

the code section as bellow:

FSM: process(clk_in, pre_state, a_serve, b_serve)
begin
--if clk_in'event and clk_in = '0' then
ball_pos_temp <= (others => '0');
a_inc <= '0';
b_inc <= '0';
error <= '0';
case pre_state is
when st_server =>
if a_serve = '1' then
a_s <= '1';
b_s <= '0';
next_state <= st_0;
elsif b_serve = '1' then
b_s <= '1';
a_s <= '0';
next_state <= st_6;
else
next_state <= st_server;
error <= '1';
a_s <= '0';
b_s <= '0';
end if;
when st_0 =>
ball_pos_temp(0) <= '1';
if a_s = '1' then
next_state <= st_1;
if b_catch = '1' then -- b catch the ball over net.
next_state <= st_server;
a_inc <= '1';
a_s <= '0';
b_s <= '0';
elsif a_catch = '1' then -- a serve/catch the ball 2 times.
next_state <= st_server;
b_inc <= '1';
a_s <= '0';
b_s <= '0';
end if;
elsif b_s = '1' then
if a_catch = '1' then
next_state <= st_1;
a_s <= '1';
b_s <= '0';
else -- a doesn't catch the ball
next_state <= st_server;
b_inc <= '1';
a_s <= '0';
b_s <= '0';
end if;
end if;
when st_1 =>
ball_pos_temp(1) <= '1';
if a_s = '1' then
next_state <= st_2;
if b_catch = '1' then -- b catch the ball over net
next_state <= st_server;
a_inc <= '1';
a_s <= '0';
b_s <= '0';
elsif a_catch = '1' then -- a serve/catch the ball 2 times.
next_state <= st_server;
b_inc <= '1';
a_s <= '0';
b_s <= '0';
end if;
elsif b_s = '1' then
if a_catch = '1' then
next_state <= st_2;
a_s <= '1';
b_s <= '0';
else
next_state <= st_0;
end if;
end if;

Noah

Noah wrote:

> when I compile a desing, I met the following warning(part of all):
> "Warning: Latch next_state.st_server has unsafe behavior
> Warning: Ports D and ENA on the latch are fed by the same signal
> pre_state.st_server

It means something like this:

process(enable,data)
begin
if (enable='1') then
latch<=enable XOR data;
end if;
end process;

If enable becomes inactive the value at the latch-input D might change
before the input is really closed. Therefore the new value might be sampled.

> I try to use clock to avoid the latch problem, and it works.
> but I can't understand the meaning of the warnings.

First you should get familiar with the 3 things you can model in VHDL:
combinational logic, latches and flipflops. There is a serious
difference between them.

process(a,b)
begin
if (a='1') then
logic<='0';
else logic<=b;
end if;
end process;

process(enable,data)
begin
if (enable='1') then
latch<=data;
end if;
end process;

process(async_reset,data)
begin
if (async_reset='1') then
flipflop<='0';
elsif rising_edge(clock) then
flipflop<=data;
end if;
end process;

If you "use a clock to avoid this problem" you change your circuit to
something very different.

Ralf

Ralf Hildebrandt

Thank you, Hildebrandt. I know about the combinational logic, simple latch,
and flip-flops.

but I still got confused on my code. is there any latch in following code
section? if it is, which service as the latch and how it works.

Thank you again!

Regards!
-- Noah

code section:
when st_1 =>
ball_pos_temp(1) <= '1';
if a_s = '1' then
next_state <= st_2;
if b_catch = '1' then -- b catch the ball over net
next_state <= st_server;
a_inc <= '1';
a_s <= '0';
b_s <= '0';
elsif a_catch = '1' then -- a serve/catch the ball 2 times.
next_state <= st_server;
b_inc <= '1';
a_s <= '0';
b_s <= '0';
end if;
elsif b_s = '1' then
if a_catch = '1' then
next_state <= st_2;
a_s <= '1';
b_s <= '0';
else
next_state <= st_0;
end if;
end if;

Noah

"Ralf Hildebrandt" <Ralf->
??????:...
> Noah wrote:
>
>> when I compile a desing, I met the following warning(part of all):
>> "Warning: Latch next_state.st_server has unsafe behavior
>> Warning: Ports D and ENA on the latch are fed by the same signal
>> pre_state.st_server
>
> It means something like this:
>
> process(enable,data)
> begin
> if (enable='1') then
> latch<=enable XOR data;
> end if;
> end process;
>
> If enable becomes inactive the value at the latch-input D might change
> before the input is really closed. Therefore the new value might be
> sampled.
>

one more thing, I try the above code section in QuartusII 5.1 with sp1.
it generates no such warning. though it maybe cause race condition...

maybe the coming enable and data I gave is not in a very correct way.

Regards!
-- Noah

Noah

Noah wrote:

> but I still got confused on my code. is there any latch in following code
> section? if it is, which service as the latch and how it works.

> code section:
> when st_1 =>
> ball_pos_temp(1) <= '1';
> if a_s = '1' then
> next_state <= st_2;
> if b_catch = '1' then -- b catch the ball over net
> next_state <= st_server;
> a_inc <= '1';
> a_s <= '0';
> b_s <= '0';
> elsif a_catch = '1' then -- a serve/catch the ball 2 times.
> next_state <= st_server;
> b_inc <= '1';
> a_s <= '0';
> b_s <= '0';
> end if;
> elsif b_s = '1' then
> if a_catch = '1' then
> next_state <= st_2;
> a_s <= '1';
> b_s <= '0';
> else
> next_state <= st_0;
> end if;
> end if;

Look e.g. at a_inc - you do not assign in every possible case of the
selectors a value to it. Therefore a_inc becomes a latch.

Furthermore in this piece of code a_inc gets only '1' in some cases -
without the other parts of the code it is a useless operation.

Ok, if I assume, that somewhere under some conditions you will assign
'0' to it, then you have a "muxed latch": The selector signals both open
the latch as well as chose the value that is latched. This may lead to
the discussed problems.


Ralf

Ralf Hildebrandt