Multiplexer

Hi,

I am trying to build a multiplexer. It has two select lines . When its
'11', it selects A when its '00' it selects B . Now, i do not want to
select anything else and maintain A or B at its output even the select
line changes to anything else like "01" or "10"... How can I do that .
I saw may examples and found that { when others => A <= ( others =>
'X' ) }

John.

john

Have you ever considered reading some digital systems book and/or heard
about flip-flops or latches? VHDL and it's "a lot more understandable"
with this knowledge. You shoud *really* do this.

You must use a process to save information. Flip-flops and latches are
generetade only this way. Something like:

process(clk)
begin
if clk'event and clk = '1' then
if sel_lines = "11" then
out <= a;
elsif sel_lines = "00" then
out <= b;
end if;
end if;
end process;

What you have been reading was about assyncronous logic (gates). It
won't save any value for you.

Regards,

Ricardo

john escreveu:

> Hi,
>
> I am trying to build a multiplexer. It has two select lines . When its
> '11', it selects A when its '00' it selects B . Now, i do not want to
> select anything else and maintain A or B at its output even the select
> line changes to anything else like "01" or "10"... How can I do that .
> I saw may examples and found that { when others => A <= ( others =>
> 'X' ) }
>
> John.

Rtafas

Hi Rtafas,
Thanks for ur reply! Have you ever considered to read writers like
shakespear or milton or books like Bible or Quran or intorduction to
ethics. If not, you should read them, before you die. because
engineering or sciences , did take alot of common sense from your
brain.
I had a simple confusion about the mux. I apologize that I put it on
the group. But you do not have to answer it if you think its too simple
for u. why did u bother to answer it. let it answer by other people.
Regards
John

john

john wrote:
> I am trying to build a multiplexer.

http://www.google.com/search?q=vhdl+...xample+process

Mike Treseler

Hey, calm down buddy. You sound a little nervous.

You had a doubt. I've made some suggestion, and it was a very good and
important one. You really should consider reading a good digital
systems book (that is not an offense, its a resonable hint due to your
question: you do not seem experienced in digital design and if so,
sorry then). Then I´ve replied your question with a piece of code and
I gave you a good explanation. No need for flaming.

Maybe you should take things with a more technical view than a personal
one, because no one is here to flame you. I won't give you a hug after
answering any question.

Sorry for the joke, regards

RTafas

john escreveu:

> Hi Rtafas,
> Thanks for ur reply! Have you ever considered to read writers like
> shakespear or milton or books like Bible or Quran or intorduction to
> ethics. If not, you should read them, before you die. because
> engineering or sciences , did take alot of common sense from your
> brain.
> I had a simple confusion about the mux. I apologize that I put it on
> the group. But you do not have to answer it if you think its too simple
> for u. why did u bother to answer it. let it answer by other people.
> Regards
> John

Rtafas

Hi,
I am sorry that I sounded angry or flaming. I do believe that u do need
to study those books and writers atleast once in ur lifetime for ur own
good. The materail, I mentioned is easily available at barnes and
nobles or any book shop in any counrty of the world. i will recommed
Hamlet by shakespear and bible. Please read them. Thanks again for ur
piece of code and reply.
Bye
John

john

You do not have to have an _explicit_ process to save information:

q <= d when rising_edge(clk); -- flip flop

q <= d when en = '1'; -- latch

output <= a when sel = '11' else b when sel = '00'; -- mux + latch

That said, latches are not generally a good idea in ASICs and FPGAs.

Andy


Rtafas wrote:
> Have you ever considered reading some digital systems book and/or heard
> about flip-flops or latches? VHDL and it's "a lot more understandable"
> with this knowledge. You shoud *really* do this.
>
> You must use a process to save information. Flip-flops and latches are
> generetade only this way. Something like:
>
> process(clk)
> begin
> if clk'event and clk = '1' then
> if sel_lines = "11" then
> out <= a;
> elsif sel_lines = "00" then
> out <= b;
> end if;
> end if;
> end process;
>
> What you have been reading was about assyncronous logic (gates). It
> won't save any value for you.
>
> Regards,
>
> Ricardo
>
> john escreveu:
>
> > Hi,
> >
> > I am trying to build a multiplexer. It has two select lines . When its
> > '11', it selects A when its '00' it selects B . Now, i do not want to
> > select anything else and maintain A or B at its output even the select
> > line changes to anything else like "01" or "10"... How can I do that .
> > I saw may examples and found that { when others => A <= ( others =>
> > 'X' ) }
> >
> > John.

Andy

A very good point. Have you tried using a reset? Something like:

q <= d when clk'event and clk = '1' else '0' when rst = '1';

I imagine that using a clock enable, must be this way.

q <= d when clk'event and clk = '1' and clken = '1' else '0' when rst =
'1';

If synthesizable, it is an interesting aprouch. Have you tried such
situations?


Andy escreveu:

> You do not have to have an _explicit_ process to save information:
>
> q <= d when rising_edge(clk); -- flip flop
>
> q <= d when en = '1'; -- latch
>
> output <= a when sel = '11' else b when sel = '00'; -- mux + latch
>
> That said, latches are not generally a good idea in ASICs and FPGAs.
>
> Andy
>
>
> Rtafas wrote:
> > Have you ever considered reading some digital systems book and/or heard
> > about flip-flops or latches? VHDL and it's "a lot more understandable"
> > with this knowledge. You shoud *really* do this.
> >
> > You must use a process to save information. Flip-flops and latches are
> > generetade only this way. Something like:
> >
> > process(clk)
> > begin
> > if clk'event and clk = '1' then
> > if sel_lines = "11" then
> > out <= a;
> > elsif sel_lines = "00" then
> > out <= b;
> > end if;
> > end if;
> > end process;
> >
> > What you have been reading was about assyncronous logic (gates). It
> > won't save any value for you.
> >
> > Regards,
> >
> > Ricardo
> >
> > john escreveu:
> >
> > > Hi,
> > >
> > > I am trying to build a multiplexer. It has two select lines . When its
> > > '11', it selects A when its '00' it selects B . Now, i do not want to
> > > select anything else and maintain A or B at its output even the select
> > > line changes to anything else like "01" or "10"... How can I do that .
> > > I saw may examples and found that { when others => A <= ( others =>
> > > 'X' ) }
> > >
> > > John.

Rtafas

On 14 Jun 2006 10:18:50 -0700, "john" <> wrote:

> Have you ever considered to read writers like
> shakespear or milton or books like Bible or Quran or intorduction to
>ethics. If not, you should read them, before you die. because
>engineering or sciences , did take alot of common sense from your
>brain.

It is entirely possible to be a good engineer who also possesses
common-sense and some familiarity with both high culture and
ethics. It is, however, impossible to be a good engineer
without first finding out something about what other
engineers have done in the past. Consequently, the advice
you received to consult a standard digital design text was
well-considered and highly appropriate.

As others have pointed out, it is perfectly possible to mix
Shakespeare and HDLs:

architecture soliloquy of prince_of_denmark is
signal question: bit_vector (7 downto 0);
begin
question <= X"2B" OR (NOT X"2B");
end;

Milton may be a little trickier, and of course Goedel is
in principle impossible to express in any finite
programming language
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley

"Rtafas" <> writes:

> A very good point. Have you tried using a reset? Something like:
>
> q <= d when clk'event and clk = '1' else '0' when rst = '1';
>
> I imagine that using a clock enable, must be this way.
>
> q <= d when clk'event and clk = '1' and clken = '1' else '0' when rst =
> '1';
>
> If synthesizable, it is an interesting aprouch. Have you tried such
> situations?
>

I just stuck this through Synplify, and it's fine with Andy's
original. It doesn't like yours, but it's OK with:
q1 <= '0' when rst = '1' else d1 when rising_edge(clk);
q2 <= '0' when rst = '1' else d2 when rising_edge(clk) and clken =
'1';

Anyone else care to try it on other tools? Here's the full code:

library ieee;
use ieee.std_logic_1164.all;

entity ffs is
port (
clk : in std_logic;
clken : in std_logic;
rst: in std_logic;
d,d1,d2 : in std_logic;
q, q1,q2 : out std_logic
);

end entity ffs adder;
architecture a1 of ffs adder is
begin
q <= d when rising_edge(clk);
q1 <= '0' when rst = '1' else d1 when rising_edge(clk);
q2 <= '0' when rst = '1' else d2 when rising_edge(clk) and clken = '1';
end architecture a1;

Cheers,
Martin

>
> Andy escreveu:
>
> > You do not have to have an _explicit_ process to save information:
> >
> > q <= d when rising_edge(clk); -- flip flop
> >
> > q <= d when en = '1'; -- latch
> >
> > output <= a when sel = '11' else b when sel = '00'; -- mux + latch
> >
> > That said, latches are not generally a good idea in ASICs and FPGAs.
> >
> > Andy
> >
> >
> > Rtafas wrote:
> > > Have you ever considered reading some digital systems book and/or heard
> > > about flip-flops or latches? VHDL and it's "a lot more understandable"
> > > with this knowledge. You shoud *really* do this.
> > >
> > > You must use a process to save information. Flip-flops and latches are
> > > generetade only this way. Something like:
> > >
> > > process(clk)
> > > begin
> > > if clk'event and clk = '1' then
> > > if sel_lines = "11" then
> > > out <= a;
> > > elsif sel_lines = "00" then
> > > out <= b;
> > > end if;
> > > end if;
> > > end process;
> > >
> > > What you have been reading was about assyncronous logic (gates). It
> > > won't save any value for you.
> > >
> > > Regards,
> > >
> > > Ricardo
> > >
> > > john escreveu:
> > >
> > > > Hi,
> > > >
> > > > I am trying to build a multiplexer. It has two select lines . When its
> > > > '11', it selects A when its '00' it selects B . Now, i do not want to
> > > > select anything else and maintain A or B at its output even the select
> > > > line changes to anything else like "01" or "10"... How can I do that .
> > > > I saw may examples and found that { when others => A <= ( others =>
> > > > 'X' ) }
> > > >
> > > > John.
>

--

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Martin Thompson