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06-14-2006, 10:44 AM
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#1 |
vhdl generate related
how do i give a component portmap statement inside a generate
statement? i need to instantiate a component n no. of times the label is in the syntax so how i add that in the code? pavithrashinde@gmail.com |
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06-14-2006, 05:29 PM
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#2 |
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Posts: n/a
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Re: vhdl generate related
wrote:
> how do i give a component portmap statement inside a generate > statement? http://groups.google.com/groups?q=vh...e+unique+label Mike Treseler |
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